Modeling Of STT-MRAM And Design Of Low Power STT-MRAM Write Circuit

Memory,which is an effective data storage chip,is a key part of the integrated circuit chip industry,as well as an essential part of electronic equipment.With the development of portable electronic devices,such as mobile phone,pad,wireless bluetooth headset,electronic devices is increasing function and stagnant battery technology to produce the contradiction,so in the circuit design level,low power consumption technology becomes more and more important,use nonvolatile memory instead of non-volatile memory is a good solution,but the existing mainstream nonvolatile memory such as FLASH,slow to read and write,write power consumption is too big to replace the application of volatile merory,sunch as SRAM and DRAM.Spin transfer torque magnetic random access memory(STT-MRAM)as an emerging nonvolatile memory,It has excellent characteristics such as high integration,faster reading and writing speed,unlimited erasable times,long data retention time,anti-irradiation and so on.It is the most promising representative of the next generation of universal memory.However,there are still some problems in the application of STT-MRAM in the low-power circuit design.Although its non-volatility can ensure that its static power consumption is almost zero,the current energy consumption during writing operation is too large,which falls short of the power gap between the main-line memory,such as SRAM and DRAM.Aiming at the problem of excessive write power consumption of STT-MRAM,the main contents of this dissertation are as follows:1)The state of the art of STT-MRAM domestic and overseas is investigated,and summarized the two typical challenges in the design of STT-MRAM read-write circuits.Then introduced the development history of spintronics,and mainly explained tunneling magnetoresistive effect and spin transfer torque effect,which are the key theories of STTMRAM application.Through the analysis of the MTJ reverse mechanism and core storage of STT-MRAM element modeling principle of the MTJ,the MTJ model which is compatible with Cadence is set by Verilog-A.It can be used to simulate in the follow-up circuit as well as provide modeling idea to the future researchers.2)Designed a “real-time termination” STT-MRAM write circuit,conventional writing since the termination of the monitoring module is composed of many digital logic gates,the area and delay cost is high at the same time,this work puts forward a monitoring to the potential of the branch nodes rather than a comparison of the data before and after,greatly simplifies the complexity of the monitoring circuit,the reuse of the read&write circuit technology is used at the same time,and also reduces the area overhead.Compared with the traditional write driver circuit,the "real-time self-terminatiion" write circuit can save 83.1% of the write energy consumption,which is only 0.314 p J/bit,under the condition of 25℃ and process corner of TT,which can greatly reduce the dynamic power consumption of STT-MRAM circuit.