Package Structure Design And Process Development For MOSFET Chip Based On Molded Interconnect System Technology

With the improvement of chip integration,the interconnection methods of lead frame and substrate in microelectronic packaging devices have gradually become the bottleneck of the development of the integrated circuit industry.Although the fan-out packaging uses redistribution layer(RDL)technology to open up a new path for interconnection,technical problems such as warpage and chip offset in the process make it difficult to promote this packaging solution.Aiming at the optimization of interconnection technology in fan-out packaging,this paper proposes a chip package structure design and process plan suitable for terminal integration of MOSFET devices based on molded interconnect system(MIS)and through finite element simulation methods,and is carried out through experiments.The verification aims to find a low-cost device manufacturing method that avoids the problems of chip offset and lithography alignment accuracy,and improves the production efficiency of fan-out packaged devices.The research content includes the following aspects:(1)A packaging scheme based on molded interconnect system is proposed.The scheme is used to integrate the gate,source and drain of the MOSFET device into the same plane.Use a single wire bonding method between the chip gate and the lead frame pins to avoid the problem of lithography accuracy;use the method of covering the entire layer of copper on the surface of the stepped plastic structure instead of using lithography equipment to make the redistribution layer through lithography patterns in order to reduce the packaging cost introduced by photolithography technology;the chip source is interconnected with the remaining pins of the lead frame by making blind holes and copper layers on the surface of the plastic packaging material,thereby reducing the packaging thickness and enhancing the heat dissipation performance.(2)Take a MOSFET chip as the package object,limit the relevant design specifications,and design the package structure and process flow according to the requirements of the design specifications.The main content of the package structure design includes four parts:lead frame design drawing,wire bonding design drawing,shape and overall design drawing.The content of the process flow is mainly three packaging schemes that realize interconnection by changing the mold,adhesive film and photolithography pattern.(3)Based on the finite element method,the warpage and stress,junction temperature and thermal resistance of the three package structure schemes are verified and analyzed.The simulation results show that the thermal stress and thermal performance of the three schemes have their own advantages and disadvantages.The solution realized by the photolithography pattern has the best heat dissipation performance but the largest warpage value,but the overall process and manufacturing conditions and usage requirements are met;the single variable simulation analysis method is used for the package structure solution realized by changing the mold,so that each package the influence of structure and material parameters on package warpage and junction temperature and thermal resistance has intuitive performance.The comprehensive results show that the decisive factor affecting package warpage is the thermal expansion coefficient of the material.The closer the thermal expansion coefficient between the materials is,the smaller the warpage value will be.In addition,the greater the thickness of the plastic package,the lower the degree of warpage,while other parameters have little effect on the degree of warpage;in terms of thermal performance,the power consumption of the chip has a huge impact on the junction temperature of the chip,and the higher the power consumption,the higher the corresponding junction temperature.The most critical factor affecting thermal resistance is the thermal conductivity of the material.The greater the thermal conductivity of the material,the stronger the thermal conductivity of the material,and the smaller the thermal resistance.(4)Based on package design and simulation analysis,the experimental process of the packaging process has been completed.The experimental process includes MOSFET chip soldering,chip pad wiring,adhesive film plastic packaging,drilling of the plastic packaging material surface and copper layer interconnection,and the final device cutting and shaping.The experimental results show that the process quality of each step is qualified,and the verification of the packaging process steps is completed.The packaging process scheme studied and designed in this paper can be applied to the packaging of a single MOSFET device.The simulation analysis and part of the process verification results have certain guiding significance for the development of new power device packaging.