Research On Static Learning Of Logic Circuit

With the improvement of circuit complexity and the decrease of circuit size,testing has become an urgent problem to be solved.Especially since the development of ultra-high integration,the function of system on chip is more powerful and the complexity is higher.At the same time,a series of chip verification and testing problems are also brought about.Testing has become a key factor restricting the design and application of VLSI,especially system on chip.As a part of testing,test generation is facing severe challenges.Test generation is a process of determining test pattern for a given circuit fault.Deterministic test generation in test generation is a method to generate test vectors automatically by algorithmic programs.This method is called automatic test pattern generation(ATPG).ATPG is widely used in chip production testing.As a tool for generating test vectors,ATPG can generate concise and high coverage test vectors according to the fault model of the circuit under test.However,in order to improve the test fault coverage rate of ATPG algorithm based on the traditional structured search,it needs a lot of repeated backtracking search on the circuit,which will consume a lot of test time and increase the test generation time.Static learning is performed before the start of ATPG program.The logical relationship between different gates in the circuit is obtained by logical reasoning,and the final learning result is obtained by the inverse theorem.In the past scientific research,logical reasoning has been widely used in many fields of electronic design automation(EDA).At the same time,static learning is also the basic technology of chip test generation theory.The research of this paper is carried out under the background of integrated circuit testability design.This paper proposes that static learning based on the new data structure can get the gate with logical relationship by forward reasoning and backward reasoning and gate level simulation of the circuit under test.This can effectively reduce the test generation time.The research content of this paper is based on event driven static learning.The benchmark circuit test set is taken as the research object to improve the static learning data structure.The experimental results are compared with the software running results of foreign universities,so as to verify the correctness of static learning of large-scale digital integrated circuits.The experimental results show that the algorithm has good scalability.