The Design Of ADC Digital Interface Circuit In MEMS Gyroscope

As a medium of communication between analog domain and digital domain,ADC is widely used in MEMS gyroscope.Many ADCs with different structures have been proposed to meet various practical application scenarios.SAR ADC and Sigma-Delta ADC are two common structures.In the two kinds of ADC structure,the digital interface circuit is indispensable.The digital interface circuit processes the original data and outputs the data converted by ADC.In this paper,the digital interface circuits of a 12 bit SAR ADC with calibration and a 24 bit sigma delta ADC are designed respectively.For SAR ADC,a digital circuit is designed to realize successive approximation logic and data processing;For Sigma-Delta ADC,a digital decimation filter is designed to process the output of the front-stage modulator.The SAR ADC uses a charge-type structure and uses a low-bit capacitance to calibrate the high-bit capacitance.The low-bit capacitance quantifies the high-bit capacitance to produce calibration results.Calibration uses a successive approximation process,so the calibration logic is included in the successive approximation logic.The calibration results are input into the digital code processing module for calculation and storage,and the original data is corrected when ADC works normally.Use Verilog HDL to write the RTL code of the module,verify the correctness of the function through simulation,and complete the layout after logical synthesis.At 0.11μm CMOS process,the area of the digital circuit is about 0.1mm~2,and the power consumption is about600μW.Sigma-Delta ADC is an oversampled ADC,which requires a digital decimation filter to complete 128-fold downsampling.The decimation filter consists of three subfilters cascaded.The first stage is a 5-level CIC filter used for 32-fold decimation.The second compensating filter compensates for the amplitude attenuation of the CIC filter and achieves 2-fold decimation.chooses A half-band filter is chosen for the last stage to complete the 2-fold decimation.The CIC filter uses Hogenauer structure,and the latter two filters are designed symmetrically using the polyphase decomposition principle of FIR filter.The signal-to-noise ratio of the overall decimation filter is 112.5dB by simulation.Verilog HDL is used to write RTL codes for all filters,the correctness of the functions is verified by simulation,and the layout is finished after logical synthesis.At 0.11μm CMOS process,the area of the decimation filter circuit is about6.6mm~2,and the power consumption is about 1.2mW.