Design And Verification Of SoC Chip Based On ESTT-MRAM IP

The Internet of Things drives the design trend of SoC(System on Chip)chips with low power consumption and diversified functions.At the same time,there are many application scenarios involved in the Internet of Things.Therefore,the demand for memory is everywhere in Io T,and the requirements for storage capacity,power consumption,and access speed are getting higher and higher.As an ideal device for next-generation non-volatile memory,SpinTorque Transfer Magnetic Random Access Memory(STT-MRAM)has many excellent characteristics such as high read/write speed,high density and non-volatile.It combines the outstanding advantages of low latency of random access memory and high integration of nonvolatile memory.In recent years,it has gradually become one of the research focuses of the international academic and business fields.In this paper,the main research work is specified from the aspects of SoC system architecture,storage management unit,software and hardware co-design.Firstly,analyzing the existing SoC system architecture and storage structure,the SoC chip design scheme based on the new memory eSTT-MRAM is established.And a non-hybrid storage system is constructed using eSTT-MRAM memory.At the same time,the system architecture design based on the ARM AMBA2.0 bus protocol is completed.The software and hardware co-design is used to design and plan the key modules,and the compilation of the system’s bottom-level startup code is completed correspondingly.Secondly,the low-power clock / reset management module is designed.The system clock state is managed through gated clock,clock frequency division and clock switching technologies to realize the dynamic adjustment of the chip in performance and power consumption.Moreover,the new SoC storage structure with 4Mb STT-MRAM as the core is explored.The storage management module based on eSTT-MRAM is designed to realize efficient management of programs and data by dynamic partitioning.In order to improve the data transfer rate between STT-MRAM memory and peripherals,DMA(Direct Memory Access)controller with AHB bus interface is designed,which uses methods such as channel multiplexing and state machine simplification to effectively reduce resource consumption.Finally,the FPGA prototype verification platform based on Xilinx artix-7 is built,and the verification results show that the functions of system and key modules conform to the design requirements.The chip is implemented in ASIC under the SMIC 40 nm CMOS process,with a total area of 9.48mm2.The number of equivalent gate circuits of the chip except for the memory is about 600 K,and the average power consumption is 20.01 m W@50MHz.The actual test results show that the chip meets the functional and performance requirements at the beginning of the design.