A Research On Key Technologies Of Mobile Industrial Processor Interface(MIPI)C-PHY Receiver Chip

With the rise of mobile device applications,a series of interface standard protocols developed by MIPI Alliance have been widely used,which is the basis for the standardization and modularization of the whole industry.Currently,display driver chips on the market mostly use D-PHY protocol interface.In the case that the interface transmission rate of mobile devices is limited,in order to meet the requirements of higher resolution and higher refresh rate,it can only be realized by parallel more data channels,which undoubtedly increases the area and power consumption.So,the C-PHY protocol interface with higher data transmission efficiency is the future development direction.This thesis mainly designs and studies a MIPI receiver chip analog receiver,which realizes the compatibility and configurable of D-PHY protocol and C-PHY protocol on the same pin,including high-speed receiver,low-power system circuit,power supply and bias circuit,etc.This thesis proposes a configuration method of receiving channel circuit,which can be compatible with D-PHY and C-PHY mode without changing the chip channel pins,and the switching between the two can be realized through simple configuration.In this thesis,several circuit structures of continuous time linear equalizer(CTLE)are discussed in detail,and a high speed front-end receiver circuit with adjustable compensation gain is designed by the structure of source-stage negative feedback.Different from the traditional clock data recovery(CDR)mode,this thesis proposes a simple structure of CDR circuit based on the particularity of C-PHY protocol,which can generate clock signals of each channel according to the received data,and flexibly configure clock duty cycle and sampling phase of clock and data according to the transmission environment.In order to satisfy the timing constraints,avoid the competition risks and reduce the power consumption caused by the rapid turnover of a large number of registers,a series-parallel conversion circuit is designed,so that when processing data at 1Gbps rate,the register of the critical path only needs 250 MHz clock,which greatly reduces the number of registers working at high frequencies and reduces the timing pressure.This thesis also designs a low power consumption mode circuit which can flexibly adjust the driving ability and has certain antiRF interference ability,and the LDO circuit and bias circuit which can stably supply power to the MIPI receiver.In order to reduce the temperature drift of the PLL that provides the clock for the digital circuit and improve the clock frequency stability of the digital logic control circuit over the entire operating temperature range,a high order temperature compensated bandgap reference circuit is designed and implemented,which can be used as the low temperature drift reference voltage for PLL and LDO power supply circuits.This thesis is based on 40 nm standard CMOS process,the layout design and streaming test were completed.The test results achieved all the target functions and design specifications,reaching 1.2Gsps for single channel transmission in high speed receiving mode,1Gsps per channel transmission in multi-channel simultaneous transmission.Each circuit module introduced in the design of the key performance parameters of the adjustable position can also reflect a good adaptive adjustment ability.And 15-30ppm/℃ temperature drift coefficients for band gap reference between-40 and 125℃.The results of the thesis can meet the current requirements of high-speed display data transmission.