Design And Implementation Of Enhanced Time Triggered Ethernet End System

On the basis of traditional Ethernet,time triggered Ethernet combines the technical characteristics of time synchronization function,circuit switching "dedicated circuit",limited speed and network redundancy,and provides a set of network solutions with high real-time performance,high reliability and high certainty.Because of its high real-time performance and high reliability,it is widely used in aerospace,intelligent driving and industrial control.This dissertation focuses on the design and implementation of the core transceiver of the enhanced time triggered Ethernet end system based on the actual needs of the laboratory cooperation project "implementation and design of the time triggered network end system interface module".This dissertation first introduces the relevant background of time triggered Ethernet technology and the research situation of this technology at home and abroad.Secondly,combined with the design requirements,the design scheme of the end system is given,and the working principle of the system is described in detail.Thirdly,the design scheme of DPF coprocessor,UDP / IP protocol accelerator module,data diversion,queue management,transmission scheduling,redundancy management and other key modules is described in detail.Fourthly,the function of the core module of the enhanced time triggered Ethernet system is simulated and verified.Finally,through board level test and system debugging,it is proved that the end system design scheme proposed in this dissertation can meet the design requirements,has stable performance,and achieves the expected design goal.The innovation of this dissertation is described as follows: first,the COM port and SAP port of business data are treated differently.Through logical isolation,data encryption and digital signature,the data sent by COM port is transmitted by digital signature authentication,which improves the security of business transmission;second,the data sent by COM port is transmitted by FPGA hardware through protocol stack /IP packaging liberates the software packaging pressure of the upper computer protocol stack;third,it realizes the conflict free Mixed Scheduling of multiple attribute services(time triggered services,rate limited services,traditional Ethernet services)in the network,and can meet the priority of high priority services.