Design And Implementation Of Signal Processing Scheme Of Ground Battlefield Reconnaissance Radar Based On FPGA+DSP

With the development of electronic technology,obtaining the timely dynamic feedback information has become the key to controlling the initiative of the battlefield.The continuous wave radar has high range resolution and no range blind zone,which satisfies the needs of modern battlefields,has been widely used in the field of ground reconnaissance.In this paper,the working principle of LFM continuous wave radar is analyzed and the scheme of beat signal processing is proposed.Aiming at the range-velocity coupling problem existing in the continuous wave system,the MTD-frequency domain pairing method is used to achieve target pairing in complex environments.Combining the conventional target detection method with the range-angle-Doppler clutter detection method to achieve highperformance detection through deduplication and merge.Then,introduce the implementation of the signal processing system based on FPGA+DSP architecture in detail and design the ground battlefield radar signal processing module to realize DDC,windowing operation,pulse compression,MTD,CFAR,clutter pattern detection,dot trace cohesion etc.Aiming at the unbalanced read-write efficiency problem in the process of matrix transposition,a read-write controller was designed to simplify the user interface and optimize the underlying timing.On this basis,combining the burst mechanism of DDR3 and the address mapping relationship,propose a matrix partitioning method to improve overall operating efficiency.For the MTD variable order output,a pipelined multichannel parallel detection structure is designed to realize CFAR detection.The design of resource reuse in exchange for computing performance improves the data throughput rate.Reasonable task scheduling is carried out due to the DSP multi-core architecture.Core 0 is deployed as a control core,which is responsible for completing the data transmission and reception and instruction analysis of the FPGA and terminal;Core 1 is deployed as an algorithm core,which is responsible for the realization of point trace aggregation,target detection and recognition.The optimization strategy of the hash table is used to efficiently rearrange the data to improve the real-time processing capability of the system.Finally,the design details of the signal processing board are introduced,and the module simulation and system testing results are given to complete the construction of the radar signal processing system.In the design of the data path,the multi-core of the DSP realizes inter-core communication through configuration parameters and interrupts;FPGA and DSP realize chip-level interconnection through SRIO in Direct IO mode;network packet is used to complete the board level data transmission between the signal processor and the terminal.After the program transplantation and interface debugging on the signal processing board,the whole design is tested with the radar system,which verifies the feasibility.