| Regular expressions are used to search and match strings,and their applications are very extensive,such as network intrusion detection,biological DNA sequences,and financial data risk control.With the development of the Internet of Things and the emergence of 5G technology,the data generated in life is increasing rapidly,and these data will increase to twice the original amount about every two years.In this case,the matching speed of the regular expression matching engine implemented based on the software solution of the traditional central processing unit(CPU)has long been unable to meet the actual demand,resulting in a large amount of wasteful data.Based on the above background,this thesis mainly researches and analyzes the Nondeterministic Finite Automaton(NFA)algorithm implemented by regular expression hardware.The conclusion obtained is that the previous hardware engine has achieved the fastest logic speed for processing a character in one clock cycle,and its actual processing speed of the data stream can only be improved by increasing the maximum clock frequency.However,their practicability is low,they need to be repeatedly developed,use decentralized comparators,and have low resource utilization.On this basis,the thesis will study separately from two research points,namely the realization scheme that requires high clock frequency and the realization scheme that does not require repeated development.The thesis compares the NFA algorithm with the idea of a state machine.Through exploration and experimentation,it is concluded that the idea of a state machine can be used to implement a regular expression hardware matching engine.Subsequently,the regular expressions were divided into several basic types and mixed types,and implemented through Verilog code one by one,and a set of "state machine realization engine scheme" for basic metacharacters was obtained.In addition,the thesis completes the design of a hardware engine in terms of resources and reconfigurable orientation,that is,the "reconfigurable engine scheme".According to the characteristics of regular expressions,an instruction format is designed,and the "double Reuse" circuit design.The "State Machine Realization Engine Scheme" has passed the input test,and the results obtained can meet the design requirements,and the speed is very fast,one character consumes one cycle,and the maximum clock frequency of Field Programmable Gate Array(FPGA)can reach 800 MHz,That is,the throughput rate is6.4Gbps,which is 1-2 times faster than the same type of research.The disadvantage is that it also requires repeated development.The "Reconfigurable Engine Solution" tests the sub-modules and the top layer separately,and also meets the matching requirements of the design.When the matching is not triggered,a character consumes one cycle,and when the matching is triggered,it consumes 5 to 8 cycles.Most of the operation time,so the speed is roughly close to one character consumes one cycle.When the architecture realizes the double multiplexing circuit,only three comparators are used,and the comprehensive report resource consumption is 355 Logic Elements(LE).Compared with the previous stacked design,which consumes a lot of LE,it has obvious advantages and does not require repeated development. |
