Design Of Low Voltage SRAM Based On Timing Speculation

With the rapid development of Io T and artificial intelligence applications,energy-efficient integrated circuits design methods have become important enabling technologies.The near-threshold wide-voltage design method is one of the internationally recognized technical approaches.SRAM is the bottleneck of chip working at low voltage,and faces the problem of reduced read and write static noise margin.SRAM performance is severely degraded at low voltage,and the operating frequency near threshold voltage is reduced to tens of MHz,which seriously affects the application of nearthreshold low-voltage SRAM.Timing speculative SRAM is an effective design method proposed in recent years,which can improve the low-voltage performance by more than double,but there is still a lack of universal circuits design and compiler in the world.Timing speculative SRAM circuit is designed,and the first timing speculative SRAM compiler based on the Open RAM framework is developed.Timing speculative SRAM is adopted.First of all,aiming at the problem that the offset voltage of sense amplifier increases the readout delay of timing speculative SRAM,a low offset sense amplifier structure is designed.The parallel structure of sampling tubes and latch tubes are adopted instead of the traditional series structure,which reduces sampling delay of sense amplifier.Simulation shows that offset voltage is reduced by 21.9%,and sampling delay is reduced by 34.9%.Secondly,in view of the large delay of detection circuit,hierarchical bus detection circuit is proposed.In the case of no errors of detection circuit,error detection delay is reduced by 20%.Finally,aiming at the problem of low-voltage write yield of SRAM,a negative bit line circuit based on capacitive coupling is designed.,which can generate negative bit line voltages of different levels,thereby reducing the power consumption under high voltage,and solving the stability of the column half-select cell,increasing the write yield by 18.7%.Based on the above circuit design,layout design of SRAM with a capacity of 1024×32bits is realized.In order to generate SRAM of arbitrary capacity,a low-voltage timing speculative SRAM compiler-TSSRAM is developed based on the Open RAM framework.The compiler supports word line width of 256?1024,step size of 16;bit line width of 8?64,step size of 4,and can generate complete design files(including Verilog,timing library,layout,spice netlist,etc.).Simulation results show that the SRAM with a capacity of 1024×32bits generated by TSSRAM has a write yield rate of6.23? under 0.6V voltage;compared with the same capacity memory generated by the TSMC28 nm HPC+ SRAM compiler,the read delay is reduced by 33.2%,The area is increased by 1.78%,and the power consumption is optimized by 12.4%.