Research On Fast Yield Analysis Method For SRAM Circuit

With the continuous advancement of integrated circuit manufacturing technology,the size of circuit continues to shrink,the voltage continues to decrease,and it is more and more difficult to accurately evaluate the impact of process variations on circuit performance and yield.This problem is complicated in low-voltage scenarios,especially for SRAM circuits with a very large number of repeating cells.To ensure the overall yield of the chip,the failure rate of each SRAM cell must be extremely low.For such a small probability evaluation problem,the traditional Monte Carlo method takes a long time to calculate the yield.Some common analysis methods based on importance sampling can reduce the number of sample simulations required and speed up the whole yield evaluation process,but they are not accurate.It is urgent to propose a fast yield evaluation method suitable for advanced technology and low-voltage scenarios.In response to the above problems,a parallel interactive Markov chain-based adaptive importance sampling algorithm is implemented,also called PI-MAIS,to evaluate the yield.Besides,a weighted-regression based high dimensional replacement model,named WR-HDMR,is introduced to further accelerate yield analysis.The combination of PI-MAIS and WR-HDMR is called WRIS yield analysis method.The main research work of this thesis is as follows: Firstly,the PI-MAIS algorithm improves the efficiency of collecting failed samples and reduces the amount of simulation samples required.Specifically,PI-MAIS divides the location parameter update step of the recommended distribution and the importance sampling yield calculation step into upper and lower layers.In the upper layer,multiple independent Markov Monte Carlo chains are used to update the location parameters corresponding to the recommended distribution.In the lower layer,the samples and the weights of the samples are adaptively updated.which realizes parallelization and accelerates the yield evaluation process.Secondly,the WR-HDMR model is trained to replace the relatively timeconsuming transistor-level circuit simulation program.The model expands the high-dimensional model into the sum of multiple low-dimensional terms,and selects the weighted least squares regression function as the basis function to fit The relationship between circuit process parameter variables and circuit output performance.Thirdly,the trained WR-HDMR model and the PI-MAIS algorithm are assembled to form the final WRIS algorithm.From the perspective of single simulation time,the WR-HDMR model is used to replace the circuit simulation program called during weight calculation in the PI-MAIS algorithm,speeding up the overall yield evaluation process.Finally,the accuracy and speed of the PI-MAIS algorithm and WRIS algorithm is verified by specific experiments on the SRAM cell and the sensitive amplifier.Under the experimental conditions of TSMC 28 nm process and 0.8V low voltage,the accuracy of the algorithm is compared with the standard Monte Carlo method,and the speed is compared with the HDIS algorithm and the AIS algorithm.For the SRAM bit cell circuit,the relative error of the PI-MAIS algorithm is 0.6%,and the error of the WRIS algorithm is 2.3%.Compared with the MC algorithm,HDIS algorithm and AIS algorithm,the speed of PI-MAIS algorithm is increased by 67.7 times,5.6 times and 2.3 times respectively.The WRIS algorithm is improved by 126.5 times,10.5 times and 4.3 times.For the SA sensitive amplifier circuit,the relative error of the PI-MAIS algorithm is 1.93%,and the error of the WRIS algorithm is 4.18%.Compared with the MC algorithm,HDIS algorithm and AIS algorithm,the speed of PI-MAIS algorithm is increased by 55.8 times,4.9 times and 2.1 times respectively.The WRIS algorithm has improved 114 times,9.9 times and 4.3 times.