Investigation On SOI-LDMOS With Wide Safe Operation Area For GaN Driver Chip

The GaN-based power devices show the advantages of fast switching speed and high critical electric field,and are widely used in high-frequency power electronic system.The SOI-LDMOS is the key component of level shift circuits in the gate drive IC.Improving the performance of SOI-LDMOS is of great significance to promote the frequency and reliability of Ga N power device driver chips.This thesis studies and optimizes the forward voltage drop,reverse breakdown voltage,and electrical and thermal safe operating area of SOI-LDMOS.It is found that failure under high drain voltage condition in the forward conduction phase occurring in the SOI-LDMOS is caused by Krick effect,which in turn leads to electric field peak transfering from source to drain and electric field peak exceeding the critical electric field of silicon.The thermal failure under continuous pulse conditions is caused by inner parasitic bipolar transistor（NPN）,which turns on by carriers generated from avalanche ionization and thermal excitation.Based on the failure mechanism,a novel SOI-LDMOS with partial SOI and deep oxide trench（PSOT-LDMOS）is proposed and investigated by TCAD simulations.The PSOT-LDMOS has the following characteristics:（1）on the one hand,reducing the thickness of the buried oxygen layer under the source side can widen the flow path of carriers,reduce impact ionization,and suppress the Krick effect;on the other hand,the heat dissipation capability of the source side can be enhanced,and the local temperature rise of the source side caused by impact ionization can be suppressed;（2）adding an oxide trench in the drift region at the source side can adjust the electric field distribution to make the lateral electric field distribution uniform;on the other hand,the distribution of carriers can be adjusted so that holes generated by impact ionization can flow into the source along the trench sidewall,avoiding the accumulation of carriers under the P-type body region,and inhibiting the turning on of the parasitic bipolar transistor.The simulation results demonstrate that the specific on resistance of the PSOT-LDMOS structure designed in this paper is 0.034Ω·cm²,the reverse breakdown voltage is 273V,and the threshold voltage is 1.53V.Under the condition that the gate voltage is 10V,the turn-back point voltage of the electrical safe operating area is 179.6V,the on-state breakdown voltage of the thermal safe operating area is 165V,and the safe working area is 1.2×10^-1W/μm which has been improved 41.7%compared with the conventional structure,meeting the design index of GaN power device driver chip.