Research On Critical Path Extraction Based On Statistical Static Timing Analysis

With the continuous development of integrated circuit technology,the commonly-used process node parameters have progressed from 90 nm in the early years to advanced process nodes of 28 nm and below.Low-voltage designs are increasingly used in existing integrated circuit designs.Under advanced technology and low-voltage operating conditions,the fluctuation of process parameters causes the delay of the circuit to show a statistical distribution law.The circuit path delay estimated based on the accurate static timing analysis(STA)method cannot accurately describe the timing behavior characteristics of the circuit.First,the circuit has been tansforms into a timing diagram represented by nodes and timing arcs in this thesis.The timing diagram is a Directed Acyclic Graph(DAG).Based on the basic idea of the block-based statistical time series analysis method,this paper proposes to use the characteristic parameters composed of statistical parameters to represent the characteristics of the time series arc,thereby replacing the traditional accurate value based on STA;By combining the SUM and MAX operations of path calculation and the tight probability calculation method,The dimensionality of the time series arc feature is reduced,without loss of generality,and finally a weighted directed acyclic time series diagram is generated.In this paper,for the generated DAG,the shortest path fast algorithm(Shortest Path Faster Algorithm,SPFA)algorithm is used to extract the longest path of the DAG,and at the same time,SLF(Small Label First)optimization and LLL(Large Label Last)optimization are used.Some SPFA algorithms are optimized to speed up the critical path extraction,and Yen’s deviated path algorithm is used to extract the critical path group of the circuit.In this paper,the node delay model is a first-order model and a partial normal model to verify the versatility of the path delay model and the critical path extraction algorithm proposed in this paper.The SMIC 28 nm,l0028ll＿vlpl＿3r.lib process library is used in this thesis,low voltage 0.8V,temperature 25°C,input load is 0.4f,output load is 0.1f,node delay modeling is for inverter,NAND gate and OR Not gate,the test circuit is part of C17 and C499 in the ISCAS85 reference circuit.The model and algorithm proposed in this paper are implemented in C++17,and the running platform is Windows with 2.8Ghz Intel Core CPU.The experimental results show that: in the smaller C17 circuit,compared to the Monte Carlo analysis method,the analysis method of the paper can increase the speed by more than 200% under the premise of ensuring the accuracy.In the larger part of the C499 circuit,the speed increase is greater than 200%.Compared with the Monte Carlo analysis method,the accuracy of the analysis method in the thesis meets the requirements,and the speed is increased by more than 300%.