| With the scarcity of spectrum resources in the microwave frequency band below 6 GHz,it is a trend to push wireless communications to the millimeter wave frequency band,which is expected to achieve a data rate of Tbps.At present,millimeter wave communication has been widely used in the research and practice of a new generation of broadband wireless communication.The license-free frequency band of 60 GHz is suitable for indoor short-distance broadband communication.However,the high frequency band also brings about a problem,that is,the RF front-end will produce more serious phase noise,which will affect the carrier synchronization in the communication system.This article focuses on the estimation algorithm of phase noise.In order to build the actual system,the physical layer frame structure of the IEEE 802.11 ay standard was fully referenced in the Matlab simulation stage,and finally a 60 GHz millimeter wave communication system with a Tbps throughput rate was designed and realized.The system uses single carrier(SC-FDE)transmission with frequency domain equalization.In addition,it also includes some important baseband technologies,such as channel estimation,carrier synchronization,phase noise estimation,etc.,including phase noise estimation and compensation The algorithm and its FPGA circuit module implementation is the research focus of this article.Considering the FPGA implementation,the phase noise estimation and compensation algorithm used in the actual system fully considers the effectiveness of the estimation algorithm and the requirements of reducing the complexity of the algorithm.The first chapter first introduces the research background and current situation of the subject,including the development status of 60 GHz wireless communication and the different characteristics of phase noise in the 60 GHz frequency band.Then,the 60 GHz phase noise is reviewed,including the source and influence of phase noise,and the development process of phase noise estimation algorithm.Finally,introduce the research work and structure of the thesis.The second chapter first introduces the 60 GHz wireless channel characteristics and channel model;then introduces the IEEE 802.11 ay standard physical layer frame structure,and focuses on the short training sequence and channel estimation sequence,comparing the traditional short training sequence,the traditional channel estimation sequence and the EDMG short The difference between the training sequence and the EDMG channel estimation sequence;then,the Gray sequence derivation formula in the standard and its role in the system are given,and the slight difference in the derivation formula is explained;then,the transceiver structure of the entire system is described in the form of a block diagram.Finally,the phase noise model and its generation method in the IEEE 802.11 ay standard are given.Chapter 3 first introduces the impact of phase noise on the 60 GHz SC-FDE wireless communication system,including the simulation model of the entire system and the average bit error rate(BER)of the system under the influence of phase noise;then introduces the current mainstream phase noise estimation algorithm;Finally,the phase noise estimation algorithm used in the actual system of this paper is proposed,and Matlab simulation is used to show that the algorithm can significantly improve the average bit error rate of the system.Compared with other algorithms,the algorithm used in this article takes into account the requirements of reducing the complexity of the algorithm and ensuring the integrity of the data on the basis of ensuring the effectiveness,reducing the difficulty of FPGA implementation.Chapter 4 gives a complete and detailed introduction to the specific hardware implementation details of the phase noise estimation and compensation module.The first is fixed-point simulation,which evaluates the impact on the system bit error rate when the input data is limited to 14 bit width;then,under the premise of meeting the requirements,the FPGA circuit logic design and simulation waveform design of the entire module and the test part are designed to provide implementation Basis and reference;then,complete the Verilog code writing work according to the previous design,and observe whether the logic block diagram and timing simulation waveform of the system meet the expectations in the two professional software Quartus and Modelsim;the premise that the positive results are obtained in the previous steps Next,finally,find the error between Moelsim simulation and Matlab simulation output,and calculate the ratio of this error to the Matlab simulation result to verify the correctness of the module implementation. |
