Research On High-Speed Fragmented Frame Reorganization Technique Of Satellite Ground Data Link

As an important part of the Space-Integrated-Ground Information Networks,the Satellite network transfers high-speed data services such as telemetry between satellites and earth,which are often realized through ultra-long data packets,that can reach thousands of bytes.To meet the requirements of the MTU(Maximum Transmission Unit)when transferring ultralong data packets,each node reorganizes the data packets for several times.At the same time,the satellite ground transfer has the disadvantages of high delay and high bit error rate,resulting in the disorder and packet loss of each segment in the transfer.The satellite network adopts the link-layer pre-slicing transmission mechanism to solve this problem,that the ultralong data packet is pre-cut into short sliced frames at the sending end and then transmitted through each node.Finally,the sliced frames are reorganized at the destination end,to avoid being sliced and reorganized in each node and realize the transfer of ultra-long data packets.However,there are still some problems such as high transmission delay,fragment out of order and high concurrency,which pose challenges to the realization of fragment frame reassembly.Therefore,the research on high-speed fragment frame reassembly technology at link layer will provide strong technical support for satellite network to realize satellite-based high-speed data transfer,and has important research significance.Firstly,the background and significance of the project are clarified,and the research status of fragment frame recombination technique is analyzed.Secondly,the characteristics of satellite ground transfer are analyzed,and the link-layer pre-slicing transmission mechanism is introduced.The link-layer frame structure,fragment reorganization process,and fragment transmission characteristics are further analyzed,and the design scheme of the high-speed fragment frame reorganization system is formulated combined with the design index.Aiming at the problem of fast cyclic redundancy check of segmented frames,a cyclic redundancy check algorithm based on coefficient parallelism is studied and implemented here.Aiming at the problem of fast indexing for feature information,the common fast indexing algorithms are studied,and a fast indexing algorithm based on block parallel is designed and implemented.In addition,aiming at the problem of sequential cache about out-of-order fragment frames,a cache architecture based on address mapping and a fragment frame access mechanism based on ping-pong operation are proposed.Finally,according to the top-down design combining with the system design index and key algorithm,the high-speed fragment frame reorganization system has been realized based on FPGA(Field Programmable Gate Array),and the function of each module of the system is simulated.In order to verify the system performance,this paper combined with the design index and system functional characteristics puts forward a test plan,completed the system test platform construction.The test results show that the system can support the sorting and reorganization of up to 4 Fragment frames per link-layer frame,the fragment frame reorganization with the maximum number of concurrent reorganization of 20000,the maximum timeout of each link layer frame of 300 ms,and the effective throughput of 6.375 Gbps.It has the advantage of supporting high throughput,a large number of concurrent fragment reassembly frames,and long time-delay.