Research And Design Of A Rail-to-rail Input/Output Precision Operational Amplifier Using CMOS Technology

Nowadays,electronic products are developing towards miniaturization and portability.The characteristic size of integrated circuits is getting smaller and smaller,the degree of integration is getting higher and higher,and the operating voltage of operational amplifiers is getting lower and lower.When the supply voltage decreases,the threshold voltage of FET does not decrease.At the same time,the common mode input range of the operational amplifier is becoming smaller and smaller,which makes it necessary to design a rail-to-rail input and output operational amplifier.High precision operational amplifiers with low offset are in great demand in the fields of medical devices,sensor applications,electronic scales,optical modules and gas detectors and so on.Therefore,it is necessary to design a precision operational amplifier.This thesis makes extensive research on the precision rail-to-rail input and output operational amplifier at home and abroad,analyzes the structure,working principle and performance advantages and disadvantages of rail-to-rail input and output precision operational amplifier,and designs a rail-to-rail input and output precision operational amplifier using CMOS technology.The operational amplifier designed in this thesis is a two-stage operational amplifier structure.In the first stage,the parallel complementary differential pair structure is used to realize rail-to-rail input,the dummy differential pair method is used to realize constant transconductance,and high gain is achieved with a folded cascode structure;The second stage adopts class AB structure to realize rail to rail output and translinear loop structure to provide static current for the output transistors.The low offset voltage is realized by digital trim technology;The bias circuit adopts a positive temperature coefficient generation circuit,a negative temperature coefficient generation circuit and bias current output circuit;A series circuit of nulling resistor and compensation capacitor is used to design the stability of operational amplifier.This thesis adopts 0.35μm CMOS process,and the circuit parameters are simulated by Cadence Spectre simulator.The analysis shows that the Op Amp designed in this thesis meets the design requirements of rail-to-rail input and output;By adopting digital trim technology to meet the requirements of low offset parameter,the typical simulation value of input offset voltage is 11.4μV when V_CM is low and 7.7μV when V_CM is high;The typical simulation value of input bias current is 4.8 p A;The typical simulation value of input offset current is 0.4 p A;The input common mode voltage range is 0 V～5 V;The output voltage low is no more than 780μV,and the difference between the output voltage high and the positive power rail is only 1 m V;The typical simulation value of Common-Mode Rejection Ratio is 141.0 d B;The typical simulation value of positive and negative Power Supply Rejection Ratio are 113 d B and 122 d B respectively;The typical simulation value of open-loop voltage gain is 111 d B;The typical simulation value of unit gain bandwidth is 29.1 MHz;The typical simulation value of phase margin is 68°;The typical simulation value of rising edge and falling edge slew rates are 18.4 V/μs and 32.0 V/μs respectively;The typical simulation value of settling time is 260 ns.The Op Amp designed in this thesis can meet the rail-to-rail input and output requirements,and the performance parameters also meet the parameters requirements.