| The H-bridge intelligent power driver IC integrates DMOS devices that provide power output,BJTs and diodes used for circuits such as reference sources,CMOS devices that provide logic functions,and passive devices such as resistors and capacitors.In BCD process platforms,integrated power devices are generally divided into LDMOS devices in which current flows laterally and VDMOS devices in which current flows vertically.The design of LDMOS devices is flexible,and the off-state withstand voltage can be adjusted by the length of the lateral drift region,but the current is concentrated on the surface of the drift region.The VDMOS devices current flows in the body along the vertical direction,the current is more uniform,the cell integration is higher under the same output current,so the chip area is smaller.Using integrated VDMOS devices for power devices can reduce the area of H-bridge intelligent power driver IC products and reduce conduction losses.Most of the power devices on the domestic BCD process platforms are integrated LDMOS devices,and there are few reports on the BCD process platform integrated with VDMOS devices.This thesis is focused on the BCD devices development work of an H-bridge intelligent power driver IC integrated with quasi-VDMOS.The main contents are as follows:Under the limitations of manufacturing capability and design requirements,60 V quasi-VDMOS,60 V NLDMOS,60 V PLDMOS,60 V NPN,60 V PNP,15 V NMOS,15 V PMOS,60 V diode,and 5.6 V Zener diode are designed.The epitaxial thickness,epitaxial concentration,doping conditions of JFET,Pwell,Nchs,Pchs,Pbody,NHV and PHV,gate width of integrated VDMOS device,dimension of drain side lead-out region,drift region length,channel length,accumulation region length,field plate length of 60V LDMOS devices and 15 V CMOS devices,dimensions of isolation structure and other process conditions and key dimensions are determined,BCD process compatibility and high voltage isolation and interconnection issues are evaluated.According to the simulation results,the slicing and biasing schemes are determined,and various device layouts are drawn for tapeout.After chip probing testing on the wafers,it was found that the off-state withstand voltage of the main power devices VDMOS was 114 V,the saturation current reached216.34μA·μm-1,and the cell specific on-resistance was 191.63 mΩ·mm~2;the off-state withstand voltage of the NMOS device reached 26 V,the saturation current reaches 170μA·μm-1;the NPN triode BVceo is 81 V,the amplification factor is above 100,and it can provide well current amplification capability in a large base current range;reverse breakdown voltage of high-voltage diodes reaches 100 V.The above devices all meet goals.Using the newly optimized process flow,device structures,termination structures and isolation structures,the layout area of various devices and isolation structures can be reduced.The layout area of power devices can be more than 20%smaller than the layout area drawn by the previous work while maintaining the current capability of 3 A.An integrated 60 V quasi-VDMOS BCD process platform is preliminarily formed,which can also be used for the development of products such as half-bridge,high-side and low-side switches. |
