Logic Design Of Analog Signal Comprehensive Test Module Based On Multiple Test Buses

As the complexity of electronic equipment increases,higher requirements are placed on test equipment.Therefore,modern large-scale test systems often use modular equipment with standard bus,which has many advantages such as the ability to perform collaborative testing,flexible functions,easy upgrades and a high degree of automated testing.Base on the hardware platform of the multi-test bus analog signal test module,this thesis adopts the idea of modularization,designs and implements three bus interfaces to adapt to the test systems using different communication protocols,and integrates three functions of oscilloscope,frequency meter and arbitrary waveform generator.It solves the problems of poor adaptability and single function of traditional test modules.The research content of this thesis is as follows:1.Broadband Oscilloscope logic design: Oscilloscope logic design is the focus of this thesis.In order to better collect different types of signals and improve user experience,two storage modes（normal storage mode and deep storage mode）and multiple acquisition modes（normal acquisition mode,peak mode,high resolution mode）are designed.Different storage modes correspond to different extraction schemes,and the three acquisition modes correspond to three extraction methods: uniform extraction,peak extraction and average extraction.This thesis designs different time base control schemes for different storage modes,and designs three extraction methods: uniform extraction,peak extraction and average extraction for the three acquisition modes.2.High resolution frequency meter logic design: In this paper,without adding a time expansion circuit,the clock unit inside the FPGA（Field Programmable Gate Array）is combined into a 1GHz count clock,and the high-precision frequency measurement and cycle measurement function with 1ns resolution is realized.3.Arbitrary waveform generator logic design: This thesis adopts the dual DDS（Direct Digital Synthesis）scheme of high-speed DDS and low-speed DDS.The memory in the high-speed DDS stores waveform data and is used for the generation of various standard waveforms;while the memory in the low-speed DDS stores the frequency control word,and the two DDS cooperate to realize the generation of various modulation waveforms.4.Multi-test-bus architecture design: In addition to the standard PXI and PXIe transmission control logic,this module also designs custom general bus transmission control logic.The test module of the custom universal bus interface can be connected to the test system through the backplane to achieve adaptation with other standard bus interface test systems.Through the research of the above content,this thesis realizes the adaptation to a variety of standard bus interface test systems,and realizes the functions of dual-channel oscilloscope with 2GSPS sample,frequency meter with resolution of 1ns and arbitrary waveform generator on a single-chip FPGA,which effectively reduces the module size and realizes three functions integration.