Research Of Operational Amplifier For High-Speed And High-Resolution Pipelined ADC

The Analog to Digital Convertor(ADC)is an important chip in modern electronic information system as the link between analog and digital signals.Among many analog-to-digital converter architectures,pipelined ADC achieves a good compromise in terms of accuracy,speed,and power consumption.Therefore it has a wide range of applications in instrumentation and modern communications.Operational amplifier is the core module of Sample-and-Hold circuit and Multiplying-Digital-Analog-Converter in pipelined ADC,and its non-ideal factors and performance index will directly affect the overall performance of pipeline ADC system.As the main active circuit,the operational amplifier also consumes a large amount of power.The study of operational amplifiers that achieve high gain,high bandwidth,and low power consumption is important to improve the performance of pipelined ADC.The thesis first introduces the basic principle of pipelined ADC and related performance indexes,and introduces the techniques and circuits that have a significant impact on the op-amp indexes,such as the allocation of bits per stage and MDAC modules.The focus is on the theoretical analysis of the metrics that need to be met by the operational amplifier in the target ADC,a comparison of several commonly used operational amplifier topologies,and an introduction to low-power switching op-amp technology.The thesis designs an operational amplifier for a 1GS/s 14 bit pipeline ADC based on a 40 nm CMOS process with a 1.8V supply voltage.2.5bit MDAC structures are used for all sub-pipeline stages of the ADC.Considering the gain requirement of 14 bit and the differential swing of 1.6V,the op-amp adopts a two-stage architecture.To improve the current efficiency and reduce the power consumption,both the first and second stages adopt a push-pull structure with NMOS tube and PMOS tube dual inputs.The first stage amplifier uses gain bootstrap technology to improve the gain.To further reduce the average power consumption of the op-amp,a switched-capacitor dynamic bias circuit is used to partially shut down the op-amp during the sampling phase,optimizing the power consumption of the op-amp without significantly affecting the op-amp build-up characteristics.Based on the schematic design and pre-simulation iterations,the thesis completed the overall layout of the op-amp and MADC,with the op-amp layout area of about105?m×76?m and the overall MADC layout area of about 150?m×140?m.post-simulation results show that the op-amp achieves an open-loop gain of 93.3d B,a gain bandwidth product of 25.3GHz,and a phase margin of 72° at the closed-loop bandwidth.After adding the dynamic bias circuit,the average power consumption is68.4m W,which is about 28.7% lower than 96 m W without the dynamic bias circuit.The MDAC1 meets the performance requirements of SFDR greater than 75 d B and ENOB greater than 11 bits when the input signal frequency is in the range of low frequency to1.5 GHz.