Research And Design Of CMOS Voltage-Controlled Oscillator

The voltage-controlled oscillator is the core module of the communication system.It provides the local oscillation signal for transceivers and the reference clock for digital circuits.The phase noise of the oscillator will affect the sensitivity and bit error rate of the system and restrict the performance of the system.CMOS technology is widely used in integrated circuit design because of its high integration and low cost,and oscillators based on CMOS technology are also widely used.With the continuous development of communication technology and CMOS technology,the system indicators are becoming more and more stringent,and higher requirements are raised on the oscillator’s phase noise and flicker noise performance.This thesis focuses on the design of low flicker noise and high frequency low phase noise VCOs,firstly introduces the basic working principle of the VCO,specific performance indicators,and the related mechanism of phase noise and flicker noise.After that,the passive components commonly used in oscillator design are discussed,and some considerations for designing oscillators are given.Then,the research background of low flicker noise oscillator and high frequency low phase noise oscillator is proposed.Three voltage-controlled oscillators are designed accordingly.The main work of this thesis includes:1.A current-limiting tail resistor is used to decrease thermal noise and flicker noise contribution from the tail current source and its bias circuit.It can also form a high impedance in the common path,which prevents the differential pair from loading the tank during triode operation and deterioration of the phase noise of the VCO.Fabricated in180-nm CMOS,A Complementary prototype consumes 3.6-m W and achieves a PN of-115.5 d Bc/Hz at 1-MHz offset and1/f ~3PN corner of 300k Hz when operating at 5.22GHz.The oscillator can get a tuning range from 5.17 to 5.94 GHz and its figure-of-merit（Fo M）is 184d Bc/Hz.2.An oscillator based on Noise-Circulating topology used in the fractional-N phase-locked loop of 24GHz frequency modulated continuous-wave（FMCW）Radar is fabricated in 65nm CMOS.It consumes 4m W and achieves a tuning range from 22.9 to25.2GHz,1/f ~3PN corner of 300k Hz and PN of-100d Bc/Hz at 1MHz offset operating at 23.3GHz.3.An improved harmonic extraction architecture is proposed.A Class-F oscillator is designed in 65nm CMOS with a drain-source transformer with ultra-low coupling coefficient,which can get a compact area and 11d Bc subharmonic rejection at the source terminal without additional tuning.The post-layout simulation shows the tuning range is from 24.1 to 29.9GHz and the subharmonic rejection is 38d Bc with the low power high selectivity injection-locked buffer.It can achieve a1/f ~3PN corner of 100k Hz,PN of-111.7d Bc/Hz at 1MHz offset and Fo M of 191.8d Bc/Hz when operating at 24.1GHz.