Time Series Prediction Algorithm And Acceleration Based On FPGA

Time series prediction and analysis technology is very important for parameter optimization and fault early warning in industrial field.At present,there is an urgent need for the technology that can optimize the algorithm performance and on-site real-time calculation.Long Short-Term Memory(LSTM)network is capable of handling long-term dependencies,but LSTM can’t encode back to front information.Bidirectional LSTM(BiLSTM)consists of a forward LSTM that taking the input in a forward direction,and a backward LSTM that taking the input in a backwards direction.The information available in the network,that is,the available context information,can be fully utilized with the Bi-LSTM.It is an effective method for time series prediction.LSTM network for onedimensional time series prediction,Bi-LSTM network pruning algorithm and the implementation of this algorithm in FPGA platform are reasearched in this thesis.The main contents of this thesis are as follows:(1)The LSTM network for one-dimensional time series prediction,Bi-LSTM network pruning algorithm are studied and optimized.The storage resources and computational complexity of LSTM network and BiLSTM network are analyzed to find the weight matrix to be pruned.The row balanced pruning and row balanced TOPK pruning methods are discussed,and a row balanced TOPK unbalanced pruning method for BiLSTM network is proposed based on the above two regular pruning methods.The experimental results show that the proposed pruning method has better pruning effect.(2)LSTM network forward calculation module,including matrix vector calculation module,element-wise calculation module and activation function calculation module are optimized for FPGA platform.Firstly,the matrix vector multiplication operation module is designed by block parallelization.Next,the element-wise calculation process is split and pipelined.Finally,according to the characteristic of centrosymmetric activation function,the storage and implementation method are optimized.This method reduces the time period of the forward calculation process and saves the storage resources required to activate the function.(3)The pruned sparse BI-LSTM network is implemented on FPGA platform,i.e.,Zynq chip.Data splicing is used to reduce the occupation of sparse matrix storage resources.Considering the continuous character of input time series data,the buffer is used to store the historical data,and the sliding window is used to read the data in the buffer,so that the problem of repeated transmission of data is avoided and the delay is reduced.Compared with CPU,the BI-LSTM network implemented on Zynq has obvious acceleration effect.