Design And Implementation Of Reconfiguable NTT Fast Algorithm For Lattice-based Cryptography

Post-Quantum Cryptography(PQC)are able to withstand violent quantum computing attacks,replace public key encryption algorithms such as RSA and ECC on a large scale,and are closely related to the next generation of encryption needs.Lattice-based Cryptography are a representative class of ciphers in the post-quantum cipher family,with advantages such as relatively simple algorithms and high speed.The security of lattice ciphers originates from the lattice difficulty problem,and the security factor varies in different lattice ciphers.The computation speed of polynomial multiplication is the key to the performance of lattice ciphers,and fast number theoretic transform is an algorithm that can speed up the computation speed of polynomial multiplication,so it is especially important to study fast number theoretic transform for lattice ciphers.The fast number theoretic transformation algorithm is not only fast,but also easy to implement in hardware circuits.Among the methods for implementing hardware circuits,reconfigurable computation can be used to implement fast number theoretic transformation algorithms with a variety of parameters while maintaining a certain speed.In this paper,the reconfigurable fast number-theoretic transformation algorithm research and hardware design are carried out for the problem of different parameters of lattice cryptographic security,and the main research aspects are as follows.(1)Reviewing PQC standardization process,this paper analyzes and extracts the security parameters of the Lattice-based Cryptography algorithm in the standardization process with modulus and polynomial order.After analyzing and comparing the characteristics of the radix-2 decimation in time fast number theoretic transformation algorithm and the radix-2 decimation in frequency fast number theoretic transformation algorithm,this paper concludes that the butterfly operation is the core of the algorithm and investigates the current hardware design structure of the butterfly unit.Accordingly,the common logic of the butterfly operation is extracted in this paper.(2)For the radix-2 decimation in time fast number theoretic transformation algorithm,a reconfigurable butterfly operation unit is designed in this paper.This hardware unit includes reconfigurable modulo-multiplying,modulo-adding,and modulo-subtracting units.In designing the above modulo operation unit,considering from the perspective of area efficiency,this paper designs a smaller area multiplier and modulo simplification module for the modulo multiplication unit,and a general structure for the modulo addition and modulo subtraction units.This structure supports operations under multiple modular.Based on the reconfigurable butterfly unit,the hardware architecture of reconfigurable NTT is designed in this paper.This can support 24-bit modulus for modulo addition,modulo subtraction and modulo multiplication operations,and support four kinds of polynomial multiplication in terms of calculation points.(3)In this paper,the designed reconfigurable NTT architecture is implemented,and after functional simulation of the designed architecture,logic synthesis is performed.The area efficiency is obtained from the results of the logic synthesis,and the performance is evaluated against other implementations as far as the area efficiency is concerned.The reconfigurable NTT architecture designed in this paper is able to support reconfiguration operations with a bit width of 24 bits and four polynomial dimensions of the modulus.There is some improvement in performance,which also shows the high flexibility of the architecture.