Design And Implementation Of Eeg Signal Classification SOC Based On RISC-Ⅴ

EEG signal is a signal formed by the sum of post-synaptic potentials generated synchronously by a large number of neurons when electrophysiological indicators are used to record brain activity.Studying the classification of EEG signals can help people better understand the working principle of the human brain,thus promoting the development of brain science.The classification of EEG signals requires high-performance processors to quickly process and classify data,while the traditional processor instruction set architecture has problems such as high complexity,low code density,and expensive commercial authorization.The new reduced instruction set architecture RISC-Ⅴ developed in recent years is not only free and open source,simple in structure,but also has the characteristics of low power consumption and high performance,which can meet the processing requirements of EEG signal classification.Therefore,it is of great significance to study how to combine the advantages of EEG signal classification with RISC-Ⅴ to promote the development of brain-computer systems.This paper analyzes EEGNet,an EEG signal classification algorithm with compact structure and strong generalization ability,and designs and implements an EEG signal classification SOC combined with the open source RISC-Ⅴ processor.For the classification algorithm,firstly,the weight data after algorithm training is quantized to improve the calculation speed;then,the algorithm is optimized from the perspective of hardware resource utilization.In terms of loop calculation implementation,timing optimization is performed according to the characteristics of loops at each layer to reduce calculation delays;finally,the algorithm interface is synthesized according to the bus protocol to generate an EEG signal classification algorithm module.On this basis,the software and hardware collaborative design is carried out.At the hardware level,the RISC-Ⅴ processor is used as the control terminal,and the AXI bus is used to facilitate the mounting of the algorithm module.At the same time,the debugging module and the data transmission module are designed.Build a RISC-Ⅴ cross-compilation and debugging environment at the software level,as well as an embedded development environment integrating compilation environment and debugging.Finally,the SOC is deployed on the FPGA.To verify the effectiveness of the method proposed in this paper,an open EEG signal dataset published on PhysioNet was used to experimentally validate the classification algorithm module and SOC constructed in this paper.The experimental results show that the classification accuracy of the pre quantization classification algorithm is 64.94%,while the classification accuracy of the post quantization classification algorithm is 64.86%,with a decrease of only 0.08% in accuracy.Meanwhile,the EEG signal classification SOC designed and implemented in this article only takes 0.14 seconds to process 3-second EEG motion signal data,which increases the computing speed by about 3.5 times compared to the classification algorithm module on the ZYNQ platform.At the same time,it has the advantages of low power consumption and low resource utilization,and can meet the needs of real-time processing of EEG signal data.