Research On High Stable Crystal Oscillator Taming And Holding System Based On GPS 1PPS

With society’s development,the demands for the accuracy and stability of time and frequency references are increasing in various fields,such as electronic communication,control metrology,satellite navigation,national defense and military industries.Although primary frequency standard sources,such as hydrogen and cesium atomic clocks,are expensive and difficult to use on a large scale.As secondary frequency standard sources,crystal oscillators are more affordable but have inferior long-term stability.The Positioning and Timing systems,such as Global Navigation Satellite Systems and Long Wave Timing System,are equipped with multiple atomic clocks,it can provide highly accurate and stable time-frequency signals.Using the signals of Positioning and Timing systems as a reference to tame the local crystal oscillator can effectively reduce the influence of the local crystal oscillator’s aging and temperature characteristics on the frequency output.When the reference signal is lost,the holding algorithm can effectively improve the frequency drift of the local crystal oscillator.Therefore,taming and holding technology has been an important research content in the time and frequency system.This thesis studies a high-stability crystal oscillator taming and holding system based on GPS timing second pulse.The main research content and results are as follows:(1)A general plan for the taming and holding system has been designed.Based on the principle of digital phase-locked loop with negative feedback regulation,a combination of FPGA and upper computer software is used to design the taming and holding system.Using the GPS 1PPS signal as a reference,the TDC module is used to measure the time discrepancy between the GPS 1PPS and the 1PPS of local crystal oscillator.The voltage adjustment amount is obtained through conversion and uses to adjust the output frequency of the local high-stability crystal oscillator.When the GPS 1PPS signal is lost,the hold algorithm is used to compensate for the output frequency of the oscillator.(2)A high-stability crystal oscillator frequency and phase tuning algorithm model is established when the reference is locked.The Pauta method and sliding average filtering are used to eliminate data outliers and reduce data jitter.The frequency modulation part adopts a dual DAC design structure,which corresponds to coarse and fine frequency adjustment respectively.By analyzing the output characteristics of the dual DAC,a frequency difference and two DAC frequency control word frequency modulation model are established to achieve the same frequency output between the user and the reference.The phase modulation part uses a digital divider structure and establishes a phase modulation model between the phase difference and the phase control word to achieve the same phase output between the user and the reference.(3)A holding algorithm model based on the crystal oscillator frequency compensation is proposed when the reference lock is lost.The Kalman filtering method is adopted to reduce data jitter.By analyzing the frequency drift characteristics of the local oscillator,two models are established to relate the frequency control words of the two DACs to the drift of the crystal oscillator frequency and compensate for the crystal oscillator frequency,which effectively improves the problem of local oscillator output frequency drift.(4)The design of the system is tested for taming and holding performance.The tests are divided into taming performance test and holding performance test,The test results show that after taming frequency,the maximum jitter of frequency difference between the system output signal and the reference source signal is ≤±0.005Hz,and the maximum jitter of time difference is about 13.26ns.Furthermore,the frequency accuracy of the system clock is improved by three orders of magnitude from 10-7 to 10-0.After taming phase,the phase difference between the system output signal and the reference source signal is ≤±10ns,and the mean absolute value of the phase difference is about 5.159ns.When the reference signal is lost,the phase drift of the system clock within 24 hours under the holding algorithm is ≤±4us.