FPGA Hardware Implementation Of Multi-Dimensional Reconciliation Encoding With Variable Throughput

Quantum Key Distribution(QKD),based on quantum mechanics,enables both parties in communication to share a completely secure key that cannot be eavesdropped upon over a quantum channel.QKD can be divided into Continuous Variable QKD(CVQKD)and Discrete Variable QKD(DVQKD)based on the different carriers of information.Compared with DVQKD,CVQKD can be well compatible with existing communication networks,saving communication equipment costs.In the case of short distances,CVQKD has a higher key rate.However,the post-processing of CVQKD is relatively more complex,mainly including data reconciliation,generation of check bits,and privacy amplification.Due to the need for multiple iterations of decoding and complex encoding for data reconciliation,the data computation amount required by the CVQKD system is relatively high.In this case,the corresponding data post-processing speed needs to match system repetition rate,otherwise,the key rate of the system will be limited and decreases.Therefore,this paper uses Field Programmable Gate Array(FPGA)to accelerate the encoding algorithm of data reconciliation.The main contents are as follows:(1)We introduced the basic principle of QKD,and the research progress of QKD in application and theory.(2)We introduced the coherent state protocol and unconditional security of CVQKD systems.Then,we explained the basic principle of data reconciliation and the concrete process of multidimensional reconciliation in detail.(3)We proposed a multidimensional reconciliation encoding algorithm based on the FPGA with a variable data throughput,which enables the CVQKD system to be adapted to different throughput requirements.We validated the feasibility and highspeed of the algorithm by implementing the multidimensional reconciliation encoding algorithm on a Xilinx Virtex-7 FPGA.Our simulation results show that the maximum throughput can reach 4.88 M symbols/s.(4)In order to obtain the syndrome more efficiently,we designed a simplified algorithm according to the characteristics of FPGA and parity check matrix,which saves the unnecessary operation such as matrix multiplication.The simplified algorithm can adapt to different code rates.