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A Novel Power-rail ESD Clamp Circuit With A Small Capacitance

Posted on:2024-08-26Degree:MasterType:Thesis
Country:ChinaCandidate:Y N LiFull Text:PDF
GTID:2530307136493954Subject:New Generation Electronic Information Technology (Professional Degree)
Abstract/Summary:
With the development of semiconductor technology,chip failures caused by electrostatic discharge(ESD)are becoming more and more serious.How to design reliable ESD protection becomes the focus of attention.In this paper,the ESD background and related knowledge are introduced briefly,then the ESD test model,test method,failure mechanism,and protective devices are described.Finally,the circuit structure and working mechanism of two kinds of traditional trigger circuits are described in detail,and their advantages and disadvantages are analyzed.On this basis,this paper optimizes and improves some problems existing in the traditional trigger circuit:(1)In order to solve the problem of false trigger and high static power consumption in traditional circuits,an anti-false trigger clamp circuit is proposed in this paper.The basic parameters required of the circuit module are calculated by theoretical analysis.Then,the extension and complement structure of the circuit is determined.This circuit combines frequency trigger with voltage trigger successfully combining the advantages of the two trigger circuits.Due to the introduction of the diode-string to adjust the minimum starting voltage of the circuit,the circuit can avoid false trigger under the fast power-on condition.In addition,the circuit adopts a two-stage trigger structure,and the MOS tube is used as a switch to reduce the static power consumption of the diode-string under normal power-on condition.Finally,the anti-false trigger circuit is evaluated by simulating power-on conditions and equivalent HBM model.(2)Due to the problems of high transient power consumption and large layout area caused by large capacitance,a novel clamp circuit with a small capacitance is proposed based on the proposed anti-false trigger clamp circuit in this paper.Due to the small capacitance will cause the circuit turnon duration to be insufficient.This circuit uses a method of feedback and shunt mechanisms combined with a capacitance,in which a small capacitance is in parallel to a shunt nMOS controlled by another feedback nMOS.The shunt nMOS diverts the capacitance charging current,then,the turn-on duration of the circuit is prolonged.The simulation results show that the turn-on duration of the proposed circuit is long enough and could respond quickly to the ESD event.All aspects of the circuit performance are improved,which could achieve ESD protection.
Keywords/Search Tags:electrostatic discharge, clamp circuit, false trigger, small capacitance, turn-on duration
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