Research And Design Of 25～28Gb/s CMOS High-sensitivity Optical Receivers

Optical interconnection is increasingly deployed in applications such as data centers to meet the increasing bandwidth demand under the situation of high energy shortage.On the one hand,the improvement of receiver sensitivity is helpful to reduce the requirement of transmitting optical power and then reduce the optical power consumption at the transmitting end.On the other hand,the traditional optical receiving front-end circuit’s need for a high gain amplifier or multistage amplifier at a faster speed causes the optical receiver’s power consumption to rise,while the optical receiver using low bandwidth techique can improve the sensitivity at the receiving end and reduce the power consumption of the front-end circuit.Different from the problem that the integrating front-end receivers are affected by the connection of"0"and"1",and the short reset pulse of the resettable receivers limit the improvement of sensitivity,the receivers based on DFE are mainly restricted by the delay of the tap feedback loop,and the sensitivity is improved by eliminating the inter-symbol interference（ISI）introduced by the low-bandwidth front-end without enhancing the high-frequency noise.In this thesis,the standard 65nm CMOS technology is adopted to research and design two high-sensitivity optical receiver circuits based on DFE.A 25～28Gb/s optical receiver circuit with adaptive equalization and clock data recovery is designed in 65 nm CMOS technology.To maximize the sensitivity of the receiver,the analog front-end uses a low-bandwidth architecture.A decision feedback equalizer is used to recover the ISI introduced by the low-bandwidth front-end.In order to adapt to the inter-symbol interference introduced by different rates and process angles,the adaptive equalization of the signal is realized by combining the SS-LMS adaptive algorithm.The reference-less clock data recovery circuit uses a frequency discrimination loop to widen the frequency capture range,which embeds a half-rate phase detector（PD）in the equalizer to reduce power consumption and cost.The post-simulation results show that under the parasitic capacitance of the 100f F photodiode,the maximum gain of the receiving front end reaches 66d BΩ,the equivalent input noise current at 25%bandwidth is 15.3p A·Hz^-1/2,and the optical receiver sensitivity is-14.5d Bm.When the supply voltage is 1.2V,the overall power consumption of the optical receiver is 181.1m W,and the overall layout area of the receiver is 1083μm×948μm.Based on the first optical receiver,a low-power and high-sensitivity optical receiver circuit with input data of 25～28Gb/s is designed by combining quarter-rate DFE and baud rate CDR.In this circuit,a quarter-rate DFE architecture is used to improve the energy efficiency ratio of the optical receiver,and dynamic comparators and clocked latches are used to replace the current-mode logic（CML）comparators and latches that consume electricity,while amplifying the signal from rail to rail.At the same time,the CDR circuit uses baud rate sampling instead of traditional over-sampling,so that voltage controlled oscillator does not need to generate eight-phase clock signals,which further saves the cost and power consumption of the circuit.The post-simulation results show that the power consumption of the optical receiver is reduced without reducing the sensitivity of the front end of the optical receiver.When the power supply voltage is 1.2V,the overall power consumption of the optical receiver is 133.6m W,and the overall layout area of the receiver is 793μm×897μm.