The Design And Optimization Of Small-World Based Network-on-Chip In Neuromorphic Processors

Neuromorphic computing tries to construct a computing system that behave like a human brain by simulating the functioning of the nervous system.The von Neumann architecture is limited by inflexibility and the von Neumann bottleneck,while Neuromorphic computing shows promise in metrics such as power consumption and parallelism.Neuromorphic processors have been promoted as the hardware platform for neuromorphic computing,which can support large scale Spiking Neural Networks(SNNs).To properly place the increasing number of neuron cores and support the inter-core communication,so an efficient interconnect system is needed in the design of neuromorphic processors.Low-cost and flexible NoCs are the main alternatives for many neuromorphic processors.Mesh has historically been used for multi-core NoCs,however,in neuromorphic chips,computation cores are relatively small,mesh-based SNNs with high resource occupation limit the peak performance and energy efficiency.The ring topology provides a low-cost and hardware-friendly implementation.Also,NoCs that take advantage of ring topology and small-world network can reduce average distance and hardware cost.This research optimizes the interconnection and communication performance of the on-chip network,based on the characteristics of neuromorphic computing.The main work and innovation of this paper include:(1)We propose a ring-based small-world NoC for neuromorphic processors.The composite structure is superior in its low complexity and resource utilization while providing sufficient bandwidth.Moreover,we propose a routing algorithm corresponding to the proposed network by adapting to the traffic pattern retrieved from the SNN application.The experimental results show that the average packet latency and the resource utilization of the proposed network is reduced by up to 18% and 35%,compared to a regular mesh network.(2)In order to satisfy the implementations of different types of SNNs,we extend the above structure to 3D space.Building a 3D ring-based small-world NoC has been motivated by the biological brain structure.The ports and links of routers in 3D NoC are increased accordingly,which makes it easier to form deadlocks.Using the proposed turn model,deadlock-free routing can be achieved.Finally,to verify the above design and test its communication performance,we perform RTL-level simulation on it and execute it under different traffic patterns.The experimental results show that the average packet latency of the proposed NoC is reduced by up to 26%,compared to a regular mesh network.In conclusion,the proposed NoC is suitable for neuromorphic processors with different implementation since it is significant to improve the design of neuromorphic processors’ NoC for neuromorphic computing.