Design Of The Timing System For Hefei Advanced Light Facility

Hefei Advanced Light Facility(HALF)is a fourth-generation synchrotron light source based on a diffraction-limited storage ring.As one of the significant systems at HALF,the timing system coordinates and controls the various systems to complete storage ring injection by triggering in a certain sequence.Additionally,it can reduce the signal drift caused by ambient temperature change or fiber aging to ensure long-term operation stability,and offer timestamps for other systems to assure the consistency of data acquisition time.Based on the investigation of the timing system of the accelerator facilities at home and abroad,an event-driven timing system is developed based on MTCA.4 bus,taking into account the requirements of the timing systems of the electron gun,buncher,linac,injection system of the storage ring,and beam measurement at HALF.To realize arbitrary bunch filling in the storage ring,the master clock of the timing system must be phase-locked and synchronized with the storage ring RF signal.The event clock frequency of the timing system is designed to be 166.6 MHz,corresponding to a minimum adjustment step of 6 ns,which is equivalent to three times of the bucket spacing in the storage ring.By compensating the transmission delay to a programmable target delay value,the timing system can decrease the signal drift caused by the fiber length change.To obtain a complete global timestamp,the whole second data obtained from NTP or GPS is combined with the sub-second data obtained using the timestamp event counter.According to the actual location of each system and the type and number of signal paths,the layout scheme of the HALF timing system is designed.The HALF control system is a distributed control system based on EPICS.Therefore,the software of the timing system is developed based on EPICS,including Input Output Controller(IOC)driver,IOC database,and operator interface(OPI).A prototype of the timing system is developed to verify the rationality of the design scheme.The jitter of the trigger pulse signal is 19.74 ps,and the delay adjustment step and pulse width adjustment step of the trigger pulse signal are both 6 ns.The delay compensation function effectively controls the trigger pulse signal drift at about 3 ps.Additionally,the global timestamp is accurate to the ns-level.The results indicate that the HALF timing prototype system performs as expected and meets the design requirements.