Research Of Pulse-based High-frequency Ultrasonic Transceiver Equipment Based On FPGA

High frequency ultrasonic testing technology is a crucial method in many fields,including medicine,military,and materials.The distinguishing feature of high-frequency ultrasonic detection systems is their ability to emit ultrasonic signals at high frequencies,which allows for high spatial resolution.This capability is significant in fields that require clear imaging,such as medical detection and particle size detection.However,as ultrasonic signals exhibit attenuation characteristics,the detection depth decreases as the frequency increases.Moreover,application requirements vary,necessitating different ultrasonic signal frequencies,signal power,and pulse width and amplitude of the excitation signal.Therefore,the development of a high-power,narrow pulse width,and wide adaptability ultrasonic transceiver device has important research value.The research presented in this article details the system design of pulse high-frequency ultrasonic testing equipment,including the transmission circuit,reception circuit,and transceiver switching circuit.In the design of the transmission circuit,a gate drive circuit with high current and low impedance was designed to achieve fast on/off control of the field-effect transistor in the circuit.The transmitting circuit can drive ultrasonic probes ranging from1 MHz to 5MHz with an adjustable pulse width of 60 ns to 560 ns and an adjustable amplitude of 44 V to 84 V.Additionally,used AD9226 sampling chip for signal sampling and the signal gain circuit and signal sampling circuit have been designed to transmit various ultrasonic receiving signals.The key technologies for system implementation were elaborated in detail.Based on the FPGA platform,first,design a sampling control module to complete the system’s analog-to-digital conversion control and data reception of the echo signal.Secondly,design a linear accumulation averaging module to improve the signal-to-noise ratio of the signal and facilitate echo signal detection.In the implementation process of the linear accumulation average noise reduction algorithm,the system uses FIFO as the data buffer,delays the waveform data of the previous frame by one waveform time,performs the bit to bit accumulation when the next waveform data is input,and finally averages.This method can effectively suppress white noise signals.The accumulation average module can set different accumulation parameters based on actual applications or the demand for signal-to-noise ratio.The sampling data has a bit width of 12 bits and an accumulation frequency range of 1 to65535 times.In addition,the design of the sampling and frequency reduction module achieves the sampling rate adjustment function of the system by sampling data streams with a sampling rate of 50 MPS,in order to meet the requirements of different application scenarios for different sampling rates.The highest sampling rate of the system is 50 MPS,and the lowest sampling rate is 6.25 MPS.Finally,the complete system performance was tested through multiple experiments and analyzed to summarize the performance parameters of the system presented in this article and compare its performance with similar products.