Research On QR-RLS Algorithm Based Array Anti-jamming And Its FPGA Implementation

Digital Array Radar(DAR)is an important branch in the field of modern radar.It has incomparable advantages over traditional analog phased array radar.It is increasingly used in a variety of scenarios in the military and civil fields.With the rapid development of electronic information technology,the electromagnetic environment that radar is facing is becoming more and more complex,which poses a more and more serious challenge to the anti-jamming performance of a radar.Digital Array Radar(DAR)provides a lot of convenience for radar anti-jamming because of its ability of spatial signal processing(that is,array signal processing).The theoretical research of array anti-jamming has lasted for decades,and there is a fairly mature theoretical system.When considering the hardware implementation,the existing methods are mainly based on Least Mean Square(LMS)algorithm to complete the hardware deployment.Although the LMS algorithm is simple and easy to implement,its slow convergence has greatly limited its application scope.Therefore,this Thesis studies the anti-jamming method using the QR-decomposition Recursive Least Square(QR-RLS)algorithm,and studies its systolic array implementation method.The specific research contents are as follows:(1)The implementation structure of the array anti-jamming algorithm is studied.The common adaptive beamforming algorithms use matrix inversion to calculate optimal weight vectors.To avoid matrix inversion for hardware implementation,the Wiener filter structure of adaptive beamforming algorithm is deduced.Specifically,a Wiener filter structure of Minimum Variance Distortionless Response(MVDR)algorithm based on a sum-difference networkis is given.The method of solving optimal weight vector using iterative algorithm is studied.By comparing the advantages and disadvantages of different adaptive iterative algorithms,the QR-RLS algorithm,which has fast convergence and is beneficial to field programmable gate array(FPGA),is chosen.(2)The implementation of array anti-jamming algorithm on the basis of the fieldbus is studied.The implementation structure of MVDR algorithm based on sumdifference network contains only simple sum and difference operations,so its logical resource consumption is low.This thesis first studies the design and optimization of the beam-pointing module and sum-difference network module in the preprocessing section,then focuses on the FPGA implementation structure of the QR-RLS algorithm based on the systolic array,and introduces the design and implementation of each processing unit in detail.Finally,the correctness of the circuit function of the array anti-jamming algorithm of 8 array elements is verified in Xilinx’s Vivado software,and its feasibility is verified by on-board test experiments.The FPGA implementation circuit of the array anti-jamming algorithm studied in this thesis can effectively resist the jamming caused by sidelobe incidence,with fast convergence speed and good steady-state performance.The maximum operating frequency of this circuit is 221.68 MHz,and the total on-chip power consumption is about0.906 W.It can be used as an anti-jamming processing module of a digital array radar and has essential application value.