Control Strategy Optimization And Circuit Design Of Buck Converter With Medium Input Voltage And High Load

The continual advancement of information technology has enabled servers to process a greater amount of data.The load on Buck power supply chips is also increasing and the performance index requirements are getting strict.Buck convertors have a variety of loop control strategies and technologies,each with different suitable applications.For servers and data centers,where the input voltage is in the medium range and the load range is large,multi-phase interleaved parallel technology combined with a suitable loop control strategy can effectively increase the maximum load capacity,optimize heavy load efficiency,and reduce the heat dissipation pressure on the chip,and has been highly favored.This thesis examines and contrasts the benefits,design challenges and suitable application scenarios of various multi-phase Buck converter loop control strategies,such as voltage mode,ripple-based voltage mode,peak current mode,current mode COT(Constant On-Time)and hysteresis mode,considering the server power supply application,the complexity of the respective systems and number of phases suitable for the load range.Finally selecting the fixed frequency dual-phase peak current mode as the loop control strategy.After choosing control strategy,thesis presents the small signal modelling and stability design of the system based on the sample-and-hold principle and Simplis simulation software.Furthermore,suitable power device parameters are selected through mathematical model simulations and the efficiency and thermal management advantages of dual-phase Buck are discussed.Finally,discussing the specific optimization of the control strategy in the system and circuits implementation process,one is the phase switching management techniques and light load operation modes at very low loads for better efficiency-load curve,the other is clock management techniques with synchronous off-chip clocks for multiple chips parallel connection and phase interleaving,the third is inductor current sampling and sharing techniques to escape mismatch between inductor currents in two phases with different processes or temperature environments,and the fourth is dynamic ramp compensation techniques to ensure the loop stability of peak current mode under different application conditions.The entire circuit system for the dual-phase peak current-mode Buck convertor in this thesis is built and implemented in the 0.35μm BCD process,and the functions of the transistor-level circuits of the various modules associated with the control strategy optimization scheme are verified.And The system level simulation results show that it has good steady state output performance,transient response performance and load efficiency curve at input voltage 6～20V,output voltage 0.6～3.5V,frequency270 k Hz～750k Hz and output current 20 A.Under the load transient of 20A/μs,the output recovery time is less than 35μs and the change voltage is less than 60 m V.At input voltage12 V and output voltage 1V,the peak efficiency is 93.29%,which meets the design application requirements.