Research On Hardware Acceleration Method Of 3D Object Detection Algorithm Based On FPGA

Intelligent transportation is an inevitable development trend in today’s world,and it is an effective means to ensure safety,improve efficiency,optimize energy consumption,and reduce emissions.Unmanned driving technology is an important research content in the field of intelligent transportation.Among them,unmanned driving technology requires the use of 3D neural network algorithms.These algorithms process 3D data collected based on lidar,structured light,and binocular cameras,and feedback on the detection results this to the control center.In recent years,with the rapid development of 3D perception technology,3D object detection algorithms have gradually emerged.However,there are still many difficulties in the application of the algorithm,such as complex network structure,difficulty in miniaturization and portability,high power consumption,and poor accuracy.In this thesis,the quantification of the Point Pillars algorithm and the realization of hardware acceleration is carried out to solve the problems of a large number of parameters,high computational complexity,and large limitations of hardware equipment when the 3D target detection algorithm is accelerated in FPGA.The main research content of this thesis is as follows:First of all,this thesis studies the network structures and codes of the four mainstream 3D target detection algorithms and reproduces the original algorithms.Comparing various performance indicators,the Point Pillars algorithm is selected as the quantitative object for research.Second,the optimization of the Point Pillars algorithm is completed,including algorithm quantization and hardware acceleration.The Point Pillars algorithm is quantified by methods such as minimum variance,calculation graph conversion,and custom operator registration,and quantifies 32 floating points to 8-bit integers,thereby reducing the number of network operations by about 9.4 times.In terms of hardware acceleration,through methods such as loop unrolling,parallel computing,and data multiplexing,the parallel computing capability of the algorithm is improved,and the computing speed is increased by 3.22 times.Finally,burn the quantized model to the ZCU104,and complete the hardware implementation of the Point Pillars algorithm through board experiments.The results show that when the computing resource is only one-twelfth of the GPU,the FPGA board realizes 50% of the running effect of the GPU,and the accuracy only drops by1.14%.It verifies the feasibility of FPGA hardware implementation of 3D object detection algorithm,which has important practical significance for hardware acceleration of 3D object detection algorithm based on FPGA.