Study Of Sigma Delta ADC For AFE Of Energy Storage Battery Monitoring

As a bridge between physical and digital information,the Sigma Delta ADC is the best choice for analog-to-digital conversion in energy storage battery monitoring system due to advantages such as low energy consumption and high precision.The Analog Front End(AFE)for energy storage battery act as the sensing touch point between the Battery Management System(BMS)and the battery pack,monitors each real-time parameter of the battery and uses the results to estimate the battery status,which is used to avoid the battery going out of safe operating range.This dissertation investigates and designs a Sigma Delta ADC for AFE monitoring of energy storage batteries.By analyzing the structure and principle of the Sigma Delta ADC,which first uses the Sigma Delta modulator with a third-order feedforward unit quantization structure that incorporates zero optimization,the non-ideal factors of the modulator are analyzed,and the modulator is modeled and simulated in Simulink.The modelling and analysis results of the modulator are used as a guide to design the basic circuit of the modulator based on the SMIC 0.18μm process.In order to meet the design objective of high accuracy,a chopper stable circuit has been devised within the first stage integrator to reduce flicker noise and voltage disorders to the first stage integrator.The internal operational amplifier is a two-stage folded common source and common gate structure with PMOS tubes as input pairs and chopper switches are added to the input and output of the first stage to reduce 1/f noise.1-Bit quantizer is a high-speed,low-power dynamic comparator to minimise overall circuit power consumption.The final pre-modulator circuit simulation shows the SNR is 112.6d B and an Effective Number of bit(ENOB)is 18.41 bits.The digital extraction filter is a three-stage cascade of sub-filters where the extraction rate can be configured to achieve different output data rates from 312.5 Hz to 20 k Hz.The CIC filter was improved to improve its stopband attenuation;the compensation filter and half-band filter each achieved a 2-fold down-sampling.The model of the digital filter is built via Simulink and the output results are FFT transformed.The RTL-level description of the three-stage cascaded digital extraction filter is performed using the Verilog HDL language.The IIC interface module sends the ADC conversion results in serial mode to facilitate communication between the ADC and the host computer.The final simulation results show that at a sampling frequency of 2.56 MHz,a signal bandwidth of 10 k Hz and an oversampling rate of 128,after adding the zero point optimization,the SNR of the overall output of the Sigma Delta modulator after is 128.3d B and the ENOB is21.02 bits.When the output rate of the digital extraction filter is 312.3Hz,the overall output SNR is 136.1d B and the ENOB is 22.39 bits,while when the output rate is 20 k Hz,the overall output SNR is 118.3d B and the ENOB is 19.21 bits,which meets the design requirements.