Research And Design Of A Self-fault-tolerant RAM System Based On Memristor

The birth of the first electron tube brought us into an information era enabled by countless electronic devices.As described by Moore’s law,IC technology continuously scale down,so new memory devices must be studied to achieve low cost and low power for nanoscale technology for the reason that the increasingly large e-world is nurturing exponential surges in information data.RRAM is such kind of memory device which is based on memristor.It has been one of the candidates for the next generation memory devices due to its nanoscale size and non-volatile features.As a new nonlinear two-terminal passive device known as the "disappearing fourth element",the memristor can realize implication logic easily.However,the development of RRAM is limited by the current manufacturing process,for there still has some defects on the memristor units,such as large dispersion of resistance and degradation after numerous operations.This thesis studied the operation of RRAM systems,compared mainstream cell structures,analyzed the impact of unit degradation,and presented a new design of RRAM array system,which targets the reliable access of degraded units.The main work and innovation contributions are reflected in:1.A new cell structure is presented,which has the function of tolerance for the writing failure caused by the degradation of memristor.This paper studied the advantages and disadvantages of the current mainstream memristor cell structures.Introducing the consideration of the impact of degradation and failure mechanisms of the memristor on the cell’s operation reliability,the implication logic is innovatively introduced into the memory cell structure.For a high-reliability memory cell with the function of tolerance for the writing failure caused by the degradation of memristor,the working principle of the structure is analyzed from the theoretical level,and the read and write operations of the cell are simulated and verified by using the existing memristor model.2.This paper designs an architecture for the memory cell proposed,including the schematic and layout of the circuit based on the SMIC 180nm process,which are simulated and evaluated.The RRAM architecture based on the 1T2M1R memory cell is analyzed,and the functional system circuit for test is designed based on the SMIC 180nm process.Corresponding layout design,the pre-simulation and post-simulation verification of the system’s fault-tolerant read and write functions are carried out.In addition,the power and area consumption is analyzed and the comparison with other memory cells is exhibited.Finally,the self-fault-tolerant resistance memory designed in this paper has a fault-tolerant reading power consumption of 32.34mW,a write power consumption of 17.52mW and a static power consumption of 15.477μW under the conditions of TT process corner,25℃,3.3V standard operating voltage and 100MHz operating frequency,which is about 70%more than that of mainstream 1T1M memory cell,in exchange for the tolerance of the writing failure caused by the degradation of memristor unit,implementing the fault-tolerant reading and fault detection functions.