Routing Architecture And Algorithm Design Of Reconfigurable Processor Based On Hierarchical Register Chain

Coarse-Grained Reconfigurable Architecture(CGRA)is one of the ideal architectures for accelerating computation-intensive applications because of its high energy efficiency and high flexibility.As a part of computation-intensive applications,loops occupy most of the execution time and are usually mapped to CGRA for acceleration.The loop is usually transformed into a data dependency graph(DDG)and then executed on CGRA in the form of software pipelining.After scheduling and preprocessing,DDG will produce a large number of long dependencies with a delay greater than 1 cycle.In pipelined execution mode,these long dependencies will consume a lot of routing resources.Based on the consideration of power consumption,the interconnection between processing units(PEs)in CGRA is sparse,and only adjacent or nearest PEs have interconnection channels.Therefore,data routing under sparse interconnection constraints is a difficulty in CGRA software pipelining.In order to solve the above problems,the existing architecture either adopts centralized local register file(RF)for data routing in PE,or adopts distributed local registers for data routing between PEs.Data routing based on local RF requires that the long dependency’s parent nodes and child nodes are arranged in the same PE,while data routing based on distributed registers in PE will consume a large number of PE ports.Therefore,the existing methods are difficult to take into account the flexibility of operator place and the consumption of interconnection ports.In order to solve the above problems,this thesis will carry out routing friendly data routing architecture and mapping algorithm.The specific research contents are as follows:(1)Aiming at the problems of poor flexibility of data routing in PE and high consumption of data routing ports between PEs in the existing architecture,a routing friendly architecture is designed based on hierarchical register chain.By constructing a long configurable register chain from the distributed registers in PE,the hierarchical register chain between PE and within PE is realized,the port overhead of data routing is reduced,and a flexible routing channel can be provided for long dependent routing under the sparse PE interconnection constraints.(2)Based on the routing architecture proposed above,a matching data mapping algorithm is designed.By constructing timing and resource constraints,designing routing cost function,establishing data mapping optimization problem,and realizing fast and efficient data mapping compilation algorithm.Experiments show that the routing architecture proposed in this thesis not only does not significantly increase the energy consumption and area,but also has 1.19 times and 2.69 times improvement in performance,1.14 times and 3.28 times improvement in energy efficiency compared with CGRA(Hy CUBE)and traditional CGRA supporting single-cycle multi-hop routing,and the compilation time is 1.86% and 50.63% of traditional CGRA and Hy CUBE,respectively.The research results of this thesis will lay a solid foundation for the development of customized architecture in the field of computation-intensive applications from the perspective of on-chip data management.