A Clock Management Circuit Module For FPGA In 65nm CMOS

With the continuous advancement of deep submicron CMOS processes,modern digital integrated circuits are moving toward ultra-large-scale integration.For digital systems,the clock signal plays an important role in the high-speed circuits and the accurate operations.Nowadays,various building blocks and abundant routing resources are distributed in the large-scale and high-performance Field Programmable Gate Array(FPGA).The clock signal phase deviation and jitter are proved to be due to the signal transmission between the on-chip modules and to affect the overall performance of the system.To adapt to the development of FPGA,it is necessary to design a clock management module with the function of strong anti-jitter and clock skew removal.At the same time,the clock management module has become the design core of autonomous intellectual propertied FPGA chips to break the foreign monopoly.Based on the UMC 65nm CMOS process,a digital clock management circuit module applied to the FPGA chips is proposed in this thesis.According to the process characteristics and chip design specifications,the theoretical analysis and performance comparisons between PLL and DLL technology are firstly carried out,and then the architecture model of the digital clock management is proposed.Moreover,the phase detector circuit,lock signal circuit,delay locked loop circuit,digital phase shifter circuit and frequency synthesizer circuit are theoretically analyzed and designed.After that,the process of schematic design,front-end simulation,back-end simulation,layout design,DRC/LVS/PEX and other processes are conducted with Virtuoso tools.In this thesis,the overall architecture of the traditional digital phase detector is improved.The signal lockout problem of the digital phase detector caused by the phase detection dead zone and the minimum delay accuracy is solved by means of the proposed lock signal circuit,which ensure the circuit to operate correctly and orderly.The digitally controlled delay unit is proposed based on the fully differential symmetric structure,and the proposed delay locked line has the advantages of wide applicable frequency range,low clock jitter and small phase deviation.The design of digital phase shifter and frequency synthesis circuit can generate multi-phase and multi-frequency output signals,providing FPGA developers with more abundant output signal choices.According to the back-end simulation results,under the standard power supply voltage of 1.1V,the digital clock management can meet the FPGA application in50～500MHz of the input frequency.The maximum jitter of the digital delay line system is less than 38.8ps,and the phase deviation between the de-skewed signal and the feedback clock is less than 100ps.And the maximum jitter of the frequency synthesis circuit is less than 450ps,and the phase deviation is less than 200ps.The layout area of the overall circuit is about 0.089mm~2,and the circuit locking time is less than 2μs.Therefore,this digital clock management(DCM)circuit is designed to have advantages of wide frequency band,low clock jitter and low delay time in addition to meeting the design requirements,achieving the design parameters,and realizing the design functions.