Research On Circuit Design And Performance Of Non-Volatile FeRAM Based On DRAM

With the rapid development of today’s semiconductor industry,every innovation in storage technology has promoted the upgrading of corresponding electronic products,among which new memories mainly include resistive memory,magnetic memory,phase change memory and ferroelectric memory(FeRAM).Compared with other new-type memories,FeRAM has the advantages of non-volatility,low power consumption,high erasing and writing cycles,and better radiation resistance.If FeRAM is designed based on traditional random-access memory,taking into account the functions of traditional random-access memory and the performance of FeRAM,it will occupy an important position in the storage field.Compared with the traditional dynamic random access memory(DRAM)circuit,the most obvious difference in this design is that the storage components of the core circuit use ferroelectric capacitors,which mainly use the polarization effect of ferroelectric capacitors to achieve non-volatile storage functions.For DRAM that cannot be realized,its peripheral circuit refers to the existing DRAM circuit.Its peripheral circuits still use existing DRAM circuits.This paper first analyzes the limitations of existing memories,and compares them with FeRAM,fully embodying the advantages of FeRAM in all aspects of performance.Secondly,the characteristics of ferroelectric materials are analyzed,and the 1T-1C memory structure is finally used in this design by analyzing several memory cells structures.Then use the 0.13 μm CMOS process,use the ferroelectric capacitor developed by the ferroelectric process,use the accumulated DRAM development foundation and design experience to design a 32 MB FeRAM circuit,so as to achieve normal reading and writing,and finally use the Hspice simulation tool.Each module circuit of FeRAM is simulated and verified.The FeRAM circuit mainly includes a storage circuit,a global control circuit and a sense amplifier circuit.The storage circuit includes a storage array circuit,a row-oriented storage array related circuit and a column-oriented storage array related circuit,the row-oriented storage array related circuit controls the word line,and the column-oriented storage array related circuit controls the bit line,so as to select the array structure circuit storage unit.The global control circuit mainly includes an address generation circuit,a testmode generation circuit and a global voltage configuration,and two storage circuits can be configured at a time.The sense amplifier adopts a latch-type sense amplifier to amplify the stored data for reading and writing.After the circuit design is completed,the layout design,process fabrication and tape-out test are carried out.So far,the whole process of the 32 MB FeRAM test chip is completed.In the test after tape-out,the two are compared and analyzed in combination with the previous circuit simulation results to confirm that the design simulation and physical test results are consistent.Through the test analysis,it can be seen that the data written by the test chip can still be retained in the storage unit after power failure,and can achieve more than ten million times of data read and write,thus verifying the non-volatility and durability of FeRAM.The FeRAM circuit based on DRAM designed in this paper not only has fast erasing speed,many erasing times,and low energy consumption,but also has obvious advantages in nonvolatility compared with traditional DRAM,so ferroelectric memory is expected to be widely used.