| With the diversification of network services and the explosive growth of network traffic,high-speed network switches have gradually become a research hotspot in the field of communication integrated circuits at home and abroad.Network equipment research is also an important issue related to national information security.In the design of network switches,there are still many difficulties in realizing the line-speed forwarding of packets,the high-speed management of queues,the scheduling to meet the quality of service,and the high-throughput switching network.This research comes from a major technical research project of the national ministries and commissions.Aiming at the backbone network switching application,a data plane forwarding subsystem in a 100 Gbps line-speed switch is designed,focusing on the design of the queue management and scheduling subsystem and the switching fabric subsystem,including the queue manager,configurable queue scheduler,and Crossbar switching fabric.In queue management,the linked list data structure is used to organize queues,the shared buffer memory architecture is used to store the packets of the queue,and the queue pointers are maintained in register files.To meet the requirement of line-speed enqueue and dequeue,the queue management and scheduling architecture adopt five parallel packet pipeline processes,and the shortest length of each pipeline stage is the time slot of the shortest frame.The data bypass technology is adopted to solve the access conflict of pipeline resources and eliminate the waiting of pipelines.Queue scheduler,based on the queue scheduling algorithm with configurable thresholds,restricts misbehaving flows from maliciously occupying the shared buffer,and completes three scheduling algorithms:strict priority(SP),Round Robin(RR),and Deficit Weighted Round Robin(DWRR).SP algorithm can provide different services for a certain type of traffic from other traffic;RR algorithm isolates each flow in its queue,so that burst traffic can’t reduce the Qo S of other flows;DWRR algorithm accurately configures the bandwidth percentage of the output port of each service class when forwarding variable-length packets and protects different traffic.The three algorithms adapt to different network applications through parameter configuration and ensure the fairness of network traffic services.The 4*4 Crossbar of packet memory is set at the crosspoints as the switching fabric to realize packet switching.In this thesis,a simulation platform and FPGA board-level test environment are built for the switching subsystem.The simulation covers the line-speed enqueue and dequeue function points,and the functional verification of three scheduling algorithms and Crossbar switching fabric is completed.In the FPGA prototype verification platform,many shortest,longest,and random length data packets are generated by Test Center.The test results show that the queue management and scheduling subsystem can meet the requirement of packet forwarding with a line speed of 160 Gbps,the frame loss rate is close to 0%,and the end-to-end delay is 0.94μs on average.The enqueue scheduler can correctly discard packets exceeding the threshold according to the configuration,and all three dequeue scheduling algorithms can schedule packets in the expected order.Under the process corner of 0.81 V-40 ℃ SS based on UMC 28 nm CMOS process,the physical design of the switching subsystem is completed by integrating it into XDNP SoC,and its critical path delay is 2.74 ns,which meets the clock frequency requirement of 312.5 MHz in SoC.The area of the queue management subsystem is 1,107,239.8726μm~2 and that of the Crossbar switch fabric subsystem is 1,090,726.3246μm~2.The switching subsystem passes the physical verification and Formality check finally. |
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