FPGA-based Audio Data Protocol Conversion System Design For PCIe-Aurora 8/10b

With the continuous development of computer technology,the data processing capacity of the central processing unit is on an exponential rise,compared to the slower trend in the bandwidth of peripheral interfaces.The PCI bus,as a representative of the second generation of IO bus standards,is no longer able to meet the performance of increasingly complex computer systems,mainly in terms of system scalability and data transmission bandwidth.In this context,Intel has proposed the third generation IO bus standard PCIe,which has flexible scalability,high bandwidth and reasonable system architecture,making it widely used in high-speed serial communication.This paper designs a PC to fiber optic module data path,using Vivado development tools and a block design approach to implement the hardware system.The PCIe protocol data from the PC is converted to AXI protocol data using the PCIe interface on the FPGA and stored in the DDR,and then the conversion from AXI protocol data to Aurora 8/10 B protocol data is done through the fiber optic module.After this,the converted data is then looped back using optical fiber.The work in this paper consists of the following parts:(1)The three generations of IO bus technologies including PCIe are introduced,and the features and performance advantages of the PCIe bus are summarized through comparative analysis,on the basis of which the future development trend of this bus is predicted.(2)The system architecture,bus hierarchy,transaction types,packet formats and configuration space of the PCIe bus are described in detail.This is followed by an analysis of the SFP+ optoelectronic conversion module,process control mechanisms and 8/10 b coding technologies based on the Aurora bus protocol.This is followed by an in-depth analysis of the characteristics,basic components and operating principles of DDR SDRAM.Finally,the handshaking mechanism and burst read/write operations of the AXI bus protocol are investigated,and the timing diagram is studied to gain an in-depth understanding of the AXI bus protocol.(3)The structural components,working principles and FPGA selection of this system are discussed in detail.Afterwards,the important modules in the system,such as PCIe,Aurora8/10 b and DDR,are analysed and studied in depth in terms of IP architecture,application scenarios and implementation details.The verification platform is built based on Verilog language and the functional verification of XDMA,Aurora and DDR modules is successfully completed by using Modelsim and Vivado simulation tools.(4)Based on the official Xilinx driver,the XDMA driver was studied and the loading of the driver was completed on this basis.Afterwards,the board-level testing of the PCIe device read/write function was successfully completed by writing first and then reading.(5)Based on the test requirements,the upper computer C program design was completed using the Qt framework.Based on this,the application is used to manipulate the test pictures and the picture data flows into the FPGA via the PCIe interface,after which the converted data is output as optical fibre and the data is transferred to the FPGA again using an optical fibre loopback.Afterwards,the data received by the optical module is captured using the built-in ILA.By comparison,it was found that the data matched exactly with the picture data operated by the upper computer program,i.e.the verification of the FPGA-based PCIeAurora 8/10 b protocol conversion system was completed.