Research On PDW Formation And Sorting Technology Of Wideband Digital Receiver

Electronic reconnaissance receiver is often used in passive radar seeker,which is mainly composed of antennas,bandpass filters,analog mixers,IF amplifiers,ADC,digital signal processor and so on.This paper mainly studies the hardware implementation of PDW formation module and radar signal sorting module in digital signal processor.The input of PDW formation module is the digital signal output of ADC,which is processed by digital channelization,pulse feature extraction and framing,and finally forms Pulse Description Word(PWD).The input of signal sorting module is PDW,and then Emitter Description Word(EWD)is formed through the pre-and-main sorting two-stage separation structur.Finally,PDW forming module and radar signal sorting module are implemented on a FPGA+DSP digital channelized signal processor hardware platform.In addition,a radar signal sorting algorithm based on attention mechanism is proposed to adapt to future electronic warfare.The FPGA+DSP digital channelized signal processor hardware platform is composed of AD sub-card and processing boards based on FPGA+DSP architecture.The FPGA and DSP are connected through interfaces such as EMIF.In the platform,XCKU085 is selected to construct PDW formation module.The 8-channel IF sampling digital signals whose sampling frequency is 2.4GHz,frequency range of 1300MHz～2300MHz is channelized through 32 channels.The pulse characteristic parameter of the obtained IQ components,such as pulse arrival time,pulse width and carrier frequency,are extracted by CORDIC algorithm module,signal amplitude detection module,instantaneous phase difference frequency measurement and other modules.PDW is generated through the framing of these feature parameters and then is transmitted to DSP through EMIF interface.In order to facilitate the subsequent radar signal sorting by DSP,the generated PDW is combined into one channel and is sorted in time order.TMS320C6678 model is selected as DSP,which is mainly responsible for radar signal sorting.Combined with the actual requirements of the project,the pre-and-main sorting twostage separation structure is adopted.The two-level K-means algorithm is used for pre-sorting.Carrier frequency and pulse width are used as characteristic parameters to achieve the purpose of diluting pulse flow.The main sorting module adopts SDIF algorithm,which completes pulse deinterlacing based on PRI to achieve the purpose of sorting.The IPC inter-core communication is used to realize the multi-core parallel processing of radar signal sorting and shorten the processing time.The two-level K-means algorithm is completed in the primary kernel,and SDIF algorithm is completed in the primary and secondary cores.