Design Of Peripheral Digital Control Circuit Based On HfO₂ RRAM

With the development of the information age,storage technology is also advancing rapidly.To meet the needs of large-scale storage systems,new non-volatile storage devices with excellent performance have become a research hotspot in the industry.Among them,Hf O₂type RRAM resistive memory has become the focus of memory technology research at this stage due to its stable data storage features,low operating power consumption,and complete compatibility with current CMOS processes.However,because this emerging storage technology is not mature enough,the current research focus is mainly on the structure of RRAM devices,resistance mechanism,and material properties.Most of the peripheral control circuits used for testing can only realize the read and write operations of a single bit or 1byte of data,and the maximum operating frequency of commercial RRAM memory is only 10MHz.In order to realize the wide application of resistive memory in engineering and further improvement of operating performance,the design,implementation and optimization of peripheral control circuits must be paid attention to.This paper mainly focuses on the read and write logic of resistive memory.Basis on realizing the peripheral control circuit with the basic data operation amount of 1byte,the limiting factors of the memory operating frequency and write verification process are analyzed and optimized.The purpose of optimizing the peripheral digital control circuit is to increase the maximum operating frequency of the memory and reduce the time consumed by the write operation.To improve the maximum operating frequency of the RRAM memory,on the basis of optimizing the data storage scheme of the RRAM main array according to the address parity corresponding to the data,combined with the column address decoding scheme of the refined design and the read and write operation control logic of increasing the address update state,the realization of When the user sends any parity initial address,the memory can decode and address the high 7bits address information in advance and perform correct read and write operations with 2bytes of data.In addition,in order to reduce the time consumed by the write operation process,on the basis of improving the operation scheme of the RRAM reference array,combined with the optimized verification logic and the array storage data sensing scheme,the simplification of the RRAM memory write verification operation process is realized,thereby reducing the write The time the operation takes.Based on the behavioral modeling of the RRAM memory array,the Sram data buffer,and the SA sense amplifier,this paper conducts functional simulation verification of the basic peripheral digital control circuit scheme and the optimized peripheral digital control circuit scheme described in Verilog HDL language respectively.The results show that the two schemes are Correct read and write operations with the data volume of 1byte and 2bytes can be performed on the main RRAM array,respectively,and the optimized write verification logic can reduce the time consumption by about 35%per cycle operation.Using the SMIC0.13μm process library,the Design Compiler software was used to perform logic synthesis on the two peripheral digital control circuits before and after the optimization.The comparison and analysis showed that the optimized design scheme on the one hand increased the maximum operating frequency from 20MHz to 50MHz,and on the other hand the circuit area is reduced by 16%,achieving the design goal of performance optimization.