Design And Implementation Of TTE Synchronization Mechanism Based On AS6802

In recent years,with the science and technology improving,the aerospace integrated electronic system presents the development trend of networking,intelligence and integration.In order to meet higher requirements,traditional Ethernet has been unable to meet the customized needs of this industry.Under this background,Time Triggered Ethernet(TTE)technology was created.TTE technology was first proposed by Austrian TTTech Company,which adds time triggering and time synchronization services on the basis of traditional Ethernet technology.It is fully compatible with standard Ethernet and suitable for various bandwidth networks,application scenarios with different real-time requirements.The synchronization protocol of AS6802 used in TTE for network time synchronization shows excellent performance,and the time synchronization accuracy can reach the microsecond level.Because of its high bandwidth,real-time,determinism and compatibility with traditional Ethernet equipment,TTE makes up the shortcomings of traditional Ethernet attracts people’s attention more and more deeply.It will be widely used in the fields of aerospace,automobile manufacturing and industrial control in the future.However,due to the existence of foreign embargoes,embargo policies and related technical barriers,the current domestic TTE engineering implementation is relatively lacking,and mature TTE products have not yet appeared.At present,China develops vigorously in the area of aerospace industry,so increasing the research on TTE technology,especially the time synchronization technology realization,it will provide great help to the development of its aerospace industry.In order to design and implement a TTE time synchronization module that complies with the AS6802 time synchronization protocol,this thesis firstly studies the AS6802 protocol,and by referring to a large number of related literatures,the AS6802 time synchronization protocol is deeply,as well as the specific process of realizing the time synchronization of the network system and the realization of the network system are clearly described,including the relevant principles for network time synchronization achieving on the curing algorithm,compression algorithm and fault tolerance mechanism,the main algorithms and mechanisms.Then,on the basis of mastering the specific synchronization principle of the TTE network and fully testing the existing foreign TTE equipment,the time synchronization mechanism is further innovated,as well as the state machine model,corresponding state jump conditions of the key functional modules are designed.Combined with the designed synchronization state machine model,a TTE time-triggered Ethernet synchronization module based on FPGA is designed using Verilog hardware description language.The TTE time synchronization module mainly includes: receiving module,CM synchronization module,SC synchronization module,SM synchronization module and sending module.The TTE time synchronization module designed in this paper conforms to the clock synchronization algorithm defined by the protocol and the related fault-tolerant mechanism of clock synchronization,which improves the fault-tolerant ability in the process of time synchronization.Finally,the comprehensive functional simulation on designed synchronization module,verifies the PCF frame receiving module,curing module,compression module,synchronization state machine module and structure of the synchronization module were carried out by Vivado and other simulation tools,indicating the integrity of the module functionality.A test environment composed of end systems and switches is built,and board-level tests are performed on the designed synchronization module to verify the functional correctness of this design.After the system board-level testing,it proves that the designed TTE time synchronization module can realize the network synchronization accuracy lower than 100 ns,and greatly reduce the time error of synchronization by the optimized time synchronization accuracy.Since the time synchronization module designed in this paper basing on FPGA,it has the characteristics of low cost,easy portability,and strong adaptability.It can receive,process and send Ethernet protocol control frames more flexibly,which will provide solid foundation for the localization of TTE chips in the future.