High Speed Hybrid Successive Approximation Register Analog-to-Digital Converter

With the development of digital systems and modern CMOS integrated circuits,mobile communication technology and sensor technology continue to develop in the direction of high performance.Especially after the large-scale application of 5G technology and optical communication technology in emerging technologies such as Autopilot and Internet of Things(Io T).High speed,high resolution and low power consumption are urgently needed for analog-to-digital conversion.However,traditional high-speed analog-to-digital converter(ADC),such as successive approximation register ADC(SAR ADC),Pipeline ADC and Flash ADC,all have some structural disadvantages,such as:SAR ADC has low conversion speed,Flash ADC has low quantization accuracy and large power consumption,Pipeline ADC has complex structure and large power consumption,etc.This requires innovations in high-speed ADCs.Due to its simple structure and lower power consumption,SAR ADC is more suitable for advanced nanoscale CMOS processes.Therefore,hybrid ADC based on SAR ADC can better balance conversion speed,quantization accuracy and power consumption by combining the advantages of other different types of ADC,such as high-speed parallel quantization of Flash ADC and high-resolution hierarchical quantization of Pipeline ADC.Therefore,hybrid ADC based on SAR ADC has gradually become the focus of high-speed ADC research.This thesis aims at high speed and medium resolution hybrid ADC,especially the fully parallel successive approximation register ADC(Flash SAR ADC),which is studied systematically.In-depth research,analysis and innovations are made on one-step multi-bit parallel quantization technique,non-binary redundancy self-calibration technique,comparator threshold voltage amplification technique,etc.And the new 2.6-bit/cycle structure and Hardware Retirement technique are introduced.In this thesis,a novel 2-then-2.6-bit/cycle parallel quantization structure using the comparator threshold voltage amplification technique and the non-binary redundancy self-calibration technique based on integer weight is proposed.A novel single-channel 9-bit500MS/s high-speed asynchronous hybrid Nyquist Flash SAR ADC is designed,which completes system-level design,behavior-level modeling,circuit-level simulation and layout-level verification,realizing high-speed parallel analog-to-digital conversion.The hybrid architecture Flash SAR ADC uses a fully differential circuit architecture and comparator clock asynchronous timing technique.Five two-stage dynamic voltage comparators using comparator threshold voltage amplification technique and pre-amplification technique divides the quantization range into four equal parts(2-bit/cycle)and six equal parts(2.6-bit/cycle),respectively.Two capacitor DACs(CDAC)are used,one of the CDAC is the reference capacitor DAC(REF-CDAC).Because of the comparator threshold voltage amplification technique,only one REF-CDAC is needed to generate all the comparator threshold voltages required for successive approximation of the parallel quantization process.Compared with the traditional structure,it greatly reduces the number of CDAC and improves the conversion speed and quantization accuracy.The power consumption,chip area and structure complexity are also reduced.Another CDAC is the signal capacitive DAC(SIG-CDAC),which adopts the non-binary redundancy self-calibration technique based on integer weight and the splitting-switching scheme with terminal capacitor reused technique.By inserting redundancies in the four quantization cycles,the redundancy self-calibration can not only improve the quantization accuracy and conversion speed,but also make the threshold voltages of comparators in the four quantization cycles all be integer multiples of LSB,so that the bit capacitor in SIG-CDAC and REF-CDAC are integer multiples of unit capacitor.The influence of capacitor mismatch on system performance is reduced.Finally,the thermometer codes are converted into non-binary digital codes and binary digital codes in two steps,completing the whole high-speed parallel analog-to-digital conversion process.This novel hybrid Flash SAR ADC is fabricated by TSMC 65nm 1P9M 1.2V standard CMOS process and packaged by QFN-5×5-40L-P0.4.The chip’s core area of layout is0.12mm~2.When the power supply voltage is 1.2V,the sampling speed is 500MS/s,input signal frequency is Nyquist frequency and input signal swing is 2.4V,the results of post-simulation show that the SNDR is 54.20d B,SFDR is 65.32d B,ENOB is 8.71bit,ERBW is Nyquist frequency,the power consumption is 5.7m W,and the Fo M is 27.2f J/conversion-step.