Hardware Design And Implementation Of Image Denoising Algorithm Based On Non-Local Means

In modern life,digital image and video are the most convenient and effective way for people to obtain information,and their quality directly affects the accuracy of information.Smart phones,surveillance,license plate recognition,face recognition and other products in daily life are inseparable from digital image processing technology.Because the image is easily affected by environmental factors and acquisition equipment,the collected image itself contains noise,which directly affects the quality of the image.Therefore,digital image denoising plays a very important role in digital image processing.There are two main categories of digital image processing:software processing and hardware processing.Software processing often belongs to post-processing,which can not be processed in real time in the use scene.Hardware processing is the hardware of software image processing algorithm.Using the characteristics of hardware,such as parallelization,pipeline and fast speed,we can accelerate the software algorithm to meet the requirements of real-time processing.There are two common digital chip systems:ASIC and FPGA.From the perspective of engineering practice,based on the fixed-point NLM algorithm and the ASIC design process,this thesis aims to design an NLM hardware module that meets the indexes of 666 MHz clock frequency,4K/60 FPS maximum image size and TSMC 12 nm manufacturing process.Through the research on the basic knowledge of digital image denoising technology,this thesis analyzes the processing flow of the classical NLM algorithm,points out that the classical NLM algorithm can not be directly used for hardware implementation because of its large amount of calculation and hardware consumption resources,and focuses on the fixed-point NLM algorithm.The algorithm reduces the amount of computation by adjusting the search window and the number of adaptive similar blocks;The exponential operation is fixed by lookup table,the linear relationship is used to approximate the exponential relationship,and the denoising effect is evaluated in many aspects.According to the design requirements and the data path and control logic of the fixed-point NLM algorithm,the overall structure of the NLM hardware module is designed,and the functional blocks are divided.The module is pipelined with Verilog HDL language,and all modules are fully verified with UVM verification environment.The problem of code coverage is analyzed and solved to ensure the correctness of the results of the NLM module,The DC synthesis tool is used for synthesis and power consumption simulation under relevant constraints.The area report shows that the area of NLM module is 154449μm~2.The power consumption report shows that the overall power consumption of NLM module is 9.171405 m W,including dynamic power consumption of 8.778990 m W and static power consumption of0.392415 m W.The experimental test is carried out in the FPGA environment with2K/30 FPS and 90 MHz clock frequency.The results show that the NLM module can work normally in different scenarios,and the flat area and detail area have good denoising effect.The hardware design in this thesis can meet the design index.