| With the rapid development of integrated circuit industry,people have higher and higher performance requirements for processor products,resulting in the increasing circuit scale of high-performance processors and the increasing difficulty of development.Therefore,verification is becoming more and more important in the process of large-scale processor chip development.The excitation of traditional software simulation is flexible and the software simulation has strong debuggability,which has been widely used in the industry.However,for the verification of large-scale and high-performance processor system,the software simulation has some problems,such as low speed and unable to simulate the real system scene.The hardware accelerated emulation based on FPGA can directly map the circuit code to the hardware platform,build a real hardware circuit,and then run test cases to quickly complete the verification of large-scale system,which makes up for the defects of software simulation and greatly improves the efficiency of project development.Based on software simulation platform and hardware accelerated emulation platform,this thesis carries out verification research on a 64-bit high-performance processor system.The main content of this thesis is as follows:Based on the detailed analysis of the characteristics of the processor system to be tested(including processor core and interconnect module),for the L1 Cache size 64 KB,L2 Cache size 512 KB,the theoretical read/write bandwidth of interconnect modules 64 B/Cycle,read delay 21 Cycle,write delay 2 Cycle and other key performance indicators,through independent research and IP reuse,multiple modules are integrated to complete the construction of a synthesizable verification system and realize the verification of the processor under test.Firstly,the Memory Sub-System(MSS)module is developed and connected to the master port of the interconnect module,through which multiple slave devices can be expanded to build a more complex and complete verification system,which overcomes the problem of insufficient interface of the processor system to realize the authenticity of the verification system.Sixteen mature synthesizable verification system IP and two performance monitor IP are connected to the slave port of MSS.which is configured by the processor core and then send excitation to the interconnect module and monitor the data transfer in real time.Secondly,based on the integrated environment,three test cases are developed to verify the data transmission function,delay performance,bandwidth performance and computing performance of the processor system of the interconnecte module.Then,software simulation and hardware-accelerated emulation were constructed by EDA tools such as ARChitect and z Cui,and the verification of processor system was carried out based on VCS software platform and Ze Bu hardware accelerated platform respectively.Finally,based on the software simulation and hardware acceleration emulation completed the verification,by analyzing the waveform file and performance data verified the correctness of the processor system function,also test the performance of the system at the same time,the results show that when transaction transmission with data bit width of 128 Bit is carried out,under the ideal work load,The read delay stays around 23 Cycle,and the write delay stays around 2 Cycle.The read/write transaction bandwidth of the interconnect module increases gradually with the increase of the workload,and finally reaches its limit when the workload is 0.80.The maximum read transaction bandwidth is 51.89 B/Cycle.The maximum write transaction bandwidth is 47.91 B/Cycle,which basically meets the design requirements.In the performance test under the same conditions,VCS software simulation consumes 4105 seconds,while Ze Bu hardware accelerated emulation only consumes 244 seconds.Compared with VCS software platform,Ze Bu hardware acceleration platform can shorten the time of verification by 94% and meet the design requirements of 90% simulation time. |
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