Research And Implementation Of SM4 Cryptographic Algorithm Accelerator Based On Software And Hardware Co-design

The SM4 cipher algorithm is a commercial block cipher algorithm independently designed by China,and has officially become an ISO/IEC international standard in 2021.The SM4 algorithm has been widely used in the secure communication field of wireless local area network,and is an important research achievement in the field of cryptography in China.The main structure of the SM4 algorithm is a 32-round cyclic iterative operation structure of key expansion and encryption operations,Each round of iterative operations scrambles the plaintext data through linear and non-linear transformations.SM4 algorithm has clear operation structure and strong security,suitable for software and hardware implementation.This thesis studies the software and hardware co-design and implementation of the SM4 algorithm accelerator,for the hardware part,a circuit structure of the SM4 algorithm accelerator based on the key cache module is proposed and the RTL-level circuit design is completed.The key cache module added in the circuit structure of the SM4 algorithm accelerator can cache the round key data of the last four encryption operations,and search and update the key cache before each operation.If the key cache is hit,32 rounds of key data are directly output,which reduces the 32 clock cycles occupied by 32 rounds of key expansion iterative operations in the encryption process.After testing,the throughput rate of the SM4 algorithm accelerator circuit structure designed in this thsis is about 40%higher than that of the commonly used circular encryption circuit structure.Compared with the commonly used pipeline encryption circuit structure,the throughput rate is comparable,the number of FPGA look-up tables used is reduced by approximately 56%.Therefore,the circuit structure of the SM4 algorithm accelerator based on the key cache module can achieve balanced resource occupation and computing performance.In order to ensure the functional correctness of the RTL design of the SM4 algorithm accelerator hardware module,this thesis builds a verification platform based on the UVM methodology to complete the efficient and accurate verification work.The specific test cases designed in the verification platform simulate the actual operation of the SM4 algorithm accelerator,and use the VCS simulation software combined with the script automation simulation method to run the verification platform.After 300 tests of specific test cases,the encryption results of the SM4 algorithm accelerator are consistent with the output results of the reference model.The functional coverage rate of the verification platform has successfully reached 100%,and the code coverage rate has reached 99.73%,the functional correctness of the SM4 algorithm accelerator hardware module has been reliably verified.The software-hardware co-design method combines the advantages of software and hardware design to improve the application flexibility and computing performance of the system.Therefore,the software and hardware co-designed SM4 algorithm accelerator implements the key expansion,encryption operation and other modules of the SM4 algorithm with complex operations and large resource consumption through hardware circuits.Simple operation,flexible applications like message grouping,ECB/CBC encryption mode and other functions use the software programming,and complete the software program design and system implementation on this basis.In this thsis,the ZYNQ development platform is used to realize the software and hardware co-design of the SM4 algorithm accelerator,and the data of the software and hardware modules are communicated through the AXI-Lite interface.Using the SM4 algorithm accelerator co-designed with software and hardware to perform cyclic encryption 1 000 000 times on the standard plaintext and key data given by the SM4 algorithm,compared with the pure software SM4 algorithm encryption operation on the ARM processor side,the software and hardware codesigned SM4 algorithm accelerator can reduce encryption time by 45%.