Design And Implementation Of Ultra-High-Speed ADC Time-Interleaved Sampling

With the development of 5G communication technology,the speed and bandwidth of the required signals have been significantly improved in ultra-wideband systems,5G backhaul and fronthaul systems,and test systems,resulting in an increasing speed of digital signal processing.Therefore,the sampling rate of the required Analog-to-Digital Converter(ADC)is also increasing.However,due to constraints such as chip processing technology,the sampling performance of a single-chip ADC chip is slow to improve and cannot keep up with the needs of the industry.The ADC time-interleaved(TIADC)sampling technology parallels multiple channel ADCs to work alternately,so that the sampling rate of the ADC device can be multiplied,and the number of ADCs in parallel can theoretically be increased to any number of channels.However,due to the uncertainty of chip processing and integrated circuit layout,working temperature and working status,it will bring many errors to the system and affect the performance of ADC time interleaving sampling.The three main mismatch errors are respectively They are:offset mismatch,gain mismatch and sampling time mismatch.How to eliminate the three mismatch errors to improve the performance of ADC time interleaving sampling is the research focus of this technology,and it is also the focus of this thesis.Based on the above issues,the main research work of this thesis is as follows:(1)Interleaving sampling and mismatch errors analysis:First,according to the principle and implementation of ADC time interleaving sampling technology,Matlab/Simulink is used to build a dual-channel ADC time interleaving sampling system model,focusing on the analysis of the output signal waveform and spectrum.And through the analysis of the offset mismatch,gain mismatch and sampling time mismatch and the derivation of the formula,three types of mismatch errors are added to the Simulink model,and each type of mismatch exists alone or when all three types of mismatches exist.Simulations are performed to verify the effect of each mismatch on system performance by comparison with ideal-case simulation results.(2)Mismatch errors calibration algorithm design:According to the analysis results of the mismatch error,compare and improve the existing calibration scheme.First of all,the simulation calibration model is established by using Simulink,and then,according to the simulation results,the FPGA that should be suitable for the system can be comprehensively calibrated algorithm,and through synthesis and implementation,the bit file is finally generated.(3)Integrated circuit design and analysis:Analyze and improve the self-developed baseband transceiver board to support dual ADC time interleaving sampling.The system of this subject is mainly composed of FPGA,high-precision clock,Bandwidth Synthesizer and two high-speed ADC chips.The verification circuit configures the main chip registers and bus structure through FPGA to make its working state reach the expected.(4)Measured analysis of dual-channel ADC time-interleaved sampling system:On the self-developed ultra-wideband baseband transceiver board,the dual-channel ADC high-speed sampling system with 12GSPS sampling rate and 12bit resolution is realized.Download the bit files of the pre-calibration and post-calibration projects to the FPGA for sampling,analyze the sampling results of the single-frequency signal,and compare the spectrogram,dynamic parameters,and time-domain recovery waveform.Compared with the pre-calibration,the spectrum after calibration has been significantly improved,the harmonic elimination effect is better,and the dynamic parameters have been significantly improved.Among them,the ENOB for sampling a 4000MHz singlefrequency signal can reach 6.5bits.The ENOB can reach more than 6.9bits when the frequency of signal is 2000MHz.