Research And Application Of High-Performance Modular Multiplication Algorithm Based On RSD

With the popularization of computer networks and the development of information technology,information security issues have become more and more attractive.The core of information security technology is cryptography,which aims to ensure the authenticity,security,confidentiality and integrity of information in computer systems.Elliptic Curve Cryptology(ECC)is a kind of cryptographic technology with advantages in the public key cryptosystem.Because of its high security,small storage space,low bandwidth requirements,small amount of calculation,fast processing speed and short key length,it has been widely used in the international community in recent years.The main contents of this paper are as follows:(1)By studying the existing modular multiplication algorithms,it is found that although the modular multiplication algorithm based on signed numbers has improved the operation efficiency,its critical path is too long and the structure of the signed number adder used in the algorithm is more complex,using too many selectors and registers,resulting in additional hardware consumption.In order to overcome these problems,this paper improves and optimizes the existing RSD-based Montgomery modular multiplication algorithm,and proposes a high-performance RSD-based Montgomery modular multiplication algorithm based on base 4,which greatly shortens the length of the critical path and reduces hardware consumption.The algorithm proposed in this paper is modeled by Verilog,simulated by Modelsim,and synthesized on Xillinx Virtex-6 FPGA(V-6)platform.The maximum frequency of the algorithm can reach 598MHz,consuming 1278LUTs.Compared with other algorithms,the running frequency of the proposed algorithm is increased by 132%～581%and the area is 4%～133%.(2)Design the architecture of modular addition and subtraction unit,modular multiplication unit and modular inversion unit.Using a modular addition and subtraction unit and three modular multiplication units in parallel structure,the Co-z algorithm is time-sequenced to improve the efficiency of the algorithm,and can make full use of modular addition and subtraction unit and modular multiplication unit to avoid waste of resources.Finally,the hardware architecture of the ECC processing unit is designed by combining the modular inverse unit and the memory.The Verilog is used to model and simulate it with Modelsim.The Design Compiler tool is used to synthesize the architecture,and the area is 1204797.61788)μm~2.Under the TSMC55nm process library,the equivalent logic gate is 627K,and the clock frequency of the circuit can reach 500MHz.The multiplier designed in this paper can not only optimize the modular multiplication unit in speed,but also has certain advantages in area.The Co-z algorithm uses the improved multiplier to schedule it,and combines it with the scalar multiplication algorithm to design the overall hardware architecture.It has a certain degree of improvement in its running speed,algorithm parallelism and area.