Design Of CMOS Digital Power Amplifier Applied To Digital Polar Transmitter

The 5G mobile communication system is a new generation mobile communication system for the post-2020 period.As one of the core modules in the 5G wireless communication system,power amplifier plays a key role in amplifying the signal and sending it out through the antenna.The efficiency of power amplifier is directly related to the efficiency of the whole system.How to develop a new type of power amplifier with high efficiency and suitable for use in multiple frequency bands is one of the hot topics of discussion.Digital power amplifiers applied to digitally polarized transmitters have high efficiency features that analog power amplifiers under conventional transmitters cannot have,and they are also adapted to multi-band requirements that fit the needs mentioned earlier.This thesis presents the research and design of a CMOS digital power amplifier for digital polar transmitter based on a 22nm CMOS process for the Sub-6GHz band in 5G mobile communication systems.The circuit consists of a driver circuit,a decoder circuit,a dual PA cell array and a three-coil power synthesis transformer.The circuit is based on a current-mode Class D power amplifier cell,and designed employing a dual PA array,with the output accomplishing power synthesis,impedance transformation,and double-ended to single-ended signal conversion by replacing the conventional RLC parallel resonant network with an on-chip three-coil transformer,which significantly simplifies the matching circuit.Modeling and model optimization of the three-coil power synthesis transformer are completed,and a broadband side-coupled power synthesis transformer is designed on this basis.The PA cell features the differential cascode structure,and a steady-state analysis of the unit circuit structure is performed to ensure stable circuit operation.Design the driver and decoder circuits according to the performance requirements.The circuit design,pre-simulation,layout design and layout-EM hybrid simulation of the RF power amplifier are carried out using Cadence,ADS and other software.A high-speed chip test bench from Southeast University was employed to test the chip.The test results show that with 2.5V and1V supply voltage,the maximum output power reaches 25.4d Bm and the maximum drain efficiency is 28.4%in the frequency range of 2.4～5.25GHz.The size of the chip is2.170×1.289mm~2.The digital power amplifier designed in this thesis achieves the expected output power and efficiency,which can be applied to the digital polarization transmitter in the Sub-6GHz band of the 5G mobile communication system.